[
    {
        "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.",
        "Counter": "0,1,2,3,4,5,6,7",
        "CounterMask": "1",
        "EventCode": "0xcd",
        "EventName": "ARITH.FPDIV_ACTIVE",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "This event counts the cycles the floating point divider is busy.",
        "Counter": "0,1,2,3,4,5,6,7",
        "CounterMask": "1",
        "EventCode": "0xb0",
        "EventName": "ARITH.FPDIV_ACTIVE",
        "PublicDescription": "This event counts the cycles the floating point divider is busy. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts all microcode FP assists.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc1",
        "EventName": "ASSISTS.FP",
        "PublicDescription": "Counts all microcode Floating Point assists. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "ASSISTS.SSE_AVX_MIX",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc1",
        "EventName": "ASSISTS.SSE_AVX_MIX",
        "PublicDescription": "ASSISTS.SSE_AVX_MIX Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x10",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xb3",
        "EventName": "FP_ARITH_DISPATCHED.PORT_0",
        "PublicDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0] Available PDIST counters: 0",
        "SampleAfterValue": "2000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xb3",
        "EventName": "FP_ARITH_DISPATCHED.PORT_1",
        "PublicDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1] Available PDIST counters: 0",
        "SampleAfterValue": "2000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xb3",
        "EventName": "FP_ARITH_DISPATCHED.PORT_5",
        "PublicDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2] Available PDIST counters: 0",
        "SampleAfterValue": "2000003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xb3",
        "EventName": "FP_ARITH_DISPATCHED.V0",
        "PublicDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0] Available PDIST counters: 0",
        "SampleAfterValue": "2000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xb3",
        "EventName": "FP_ARITH_DISPATCHED.V1",
        "PublicDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1] Available PDIST counters: 0",
        "SampleAfterValue": "2000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xb3",
        "EventName": "FP_ARITH_DISPATCHED.V2",
        "PublicDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5] Available PDIST counters: 0",
        "SampleAfterValue": "2000003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc7",
        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
        "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc7",
        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc7",
        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
        "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x10",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc7",
        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
        "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x20",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc7",
        "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x18",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below.  Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc7",
        "EventName": "FP_ARITH_INST_RETIRED.SCALAR",
        "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x3",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc7",
        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
        "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc7",
        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
        "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of any Vector retired FP arithmetic instructions",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc7",
        "EventName": "FP_ARITH_INST_RETIRED.VECTOR",
        "PublicDescription": "Number of any Vector retired FP arithmetic instructions.  The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0xfc",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of all types of floating point operations per uop with all default weighting",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc8",
        "EventName": "FP_FLOPS_RETIRED.ALL",
        "SampleAfterValue": "1000003",
        "UMask": "0x3",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP64]",
        "Counter": "0,1,2,3,4,5,6,7",
        "Deprecated": "1",
        "EventCode": "0xc8",
        "EventName": "FP_FLOPS_RETIRED.DP",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of floating point operations that produce 32 bit single precision results [This event is alias to FP_FLOPS_RETIRED.SP]",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc8",
        "EventName": "FP_FLOPS_RETIRED.FP32",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of floating point operations that produce 64 bit double precision results [This event is alias to FP_FLOPS_RETIRED.DP]",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc8",
        "EventName": "FP_FLOPS_RETIRED.FP64",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP32]",
        "Counter": "0,1,2,3,4,5,6,7",
        "Deprecated": "1",
        "EventCode": "0xc8",
        "EventName": "FP_FLOPS_RETIRED.SP",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the total number of  floating point retired instructions.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc7",
        "EventName": "FP_INST_RETIRED.128B_DP",
        "SampleAfterValue": "1000003",
        "UMask": "0x8",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc7",
        "EventName": "FP_INST_RETIRED.128B_SP",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc7",
        "EventName": "FP_INST_RETIRED.256B_DP",
        "SampleAfterValue": "1000003",
        "UMask": "0x20",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc7",
        "EventName": "FP_INST_RETIRED.32B_SP",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc7",
        "EventName": "FP_INST_RETIRED.64B_DP",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of uops executed on floating point and vector integer store data port.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xb2",
        "EventName": "FP_VINT_UOPS_EXECUTED.STD",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc3",
        "EventName": "MACHINE_CLEARS.FP_ASSIST",
        "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
        "SampleAfterValue": "20003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc2",
        "EventName": "UOPS_RETIRED.FPDIV",
        "SampleAfterValue": "2000003",
        "UMask": "0x8",
        "Unit": "cpu_atom"
    }
]
