[
    {
        "ArchStdEvent": "L1D_CACHE_RD"
    },
    {
        "ArchStdEvent": "L1D_CACHE_WR"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
    },
    {
        "ArchStdEvent": "L1D_CACHE_INVAL",
        "Errata": "Errata AC03_CPU_41",
        "BriefDescription": "L1D cache invalidate. Impacted by errata -"
    },
    {
        "ArchStdEvent": "L1D_TLB_REFILL_RD"
    },
    {
        "ArchStdEvent": "L1D_TLB_REFILL_WR"
    },
    {
        "ArchStdEvent": "L2D_CACHE_RD"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WR"
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL_RD"
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL_WR"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
    },
    {
        "ArchStdEvent": "L2D_CACHE_INVAL"
    },
    {
        "ArchStdEvent": "L1I_CACHE_REFILL"
    },
    {
        "ArchStdEvent": "L1I_TLB_REFILL"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL"
    },
    {
        "ArchStdEvent": "L1D_CACHE"
    },
    {
        "ArchStdEvent": "L1D_TLB_REFILL"
    },
    {
        "ArchStdEvent": "L1I_CACHE"
    },
    {
        "ArchStdEvent": "L2D_CACHE"
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB"
    },
    {
        "ArchStdEvent": "L1D_TLB"
    },
    {
        "ArchStdEvent": "L1I_TLB"
    },
    {
        "ArchStdEvent": "L2D_TLB_REFILL"
    },
    {
        "ArchStdEvent": "L2I_TLB_REFILL"
    },
    {
        "ArchStdEvent": "L2D_TLB"
    },
    {
        "ArchStdEvent": "L2I_TLB"
    },
    {
        "ArchStdEvent": "DTLB_WALK"
    },
    {
        "ArchStdEvent": "ITLB_WALK"
    },
    {
        "ArchStdEvent": "L1D_CACHE_LMISS_RD"
    },
    {
        "ArchStdEvent": "L1I_CACHE_LMISS"
    },
    {
        "ArchStdEvent": "L2D_CACHE_LMISS_RD"
    }
]
