[
    {
        "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "2",
        "EventCode": "0xa3",
        "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
        "PublicDescription": "Cycles while L3 cache miss demand load is outstanding. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "6",
        "EventCode": "0xa3",
        "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
        "PublicDescription": "Execution stalls while L3 cache miss demand load is outstanding. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x6"
    },
    {
        "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc3",
        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
        "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "2",
        "EventCode": "0x47",
        "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS",
        "PublicDescription": "Cycles while L1 cache miss demand load is outstanding. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "3",
        "EventCode": "0x47",
        "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS",
        "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x3"
    },
    {
        "BriefDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "5",
        "EventCode": "0x47",
        "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS",
        "PublicDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock). Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x5"
    },
    {
        "BriefDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "9",
        "EventCode": "0x47",
        "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS",
        "PublicDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock). Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x9"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
        "Counter": "1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x400",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
        "SampleAfterValue": "53",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
        "Counter": "1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x80",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
        "SampleAfterValue": "1009",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
        "Counter": "1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x10",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
        "SampleAfterValue": "20011",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.",
        "Counter": "1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x800",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
        "SampleAfterValue": "23",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
        "Counter": "1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x100",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
        "SampleAfterValue": "503",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
        "Counter": "1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x20",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
        "Counter": "1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x4",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
        "Counter": "1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x200",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
        "SampleAfterValue": "101",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
        "Counter": "1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x40",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
        "SampleAfterValue": "2003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
        "Counter": "1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x8",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
        "SampleAfterValue": "50021",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
        "Counter": "0",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
        "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8 Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_CODE_RD.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x73C000004",
        "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FBFC00004",
        "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x104000004",
        "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_DATA_RD.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x73C000001",
        "PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FBFC00001",
        "PublicDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x104000001",
        "PublicDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x730000001",
        "PublicDescription": "Counts demand data reads that were supplied by DRAM attached to another socket. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_RFO.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x73C000002",
        "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_RFO.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3F3FC00002",
        "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x104000002",
        "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.READS_TO_CORE.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x73C004477",
        "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.READS_TO_CORE.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3F3FC04477",
        "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3F04C04477",
        "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.  It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x70CC04477",
        "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.  It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x104004477",
        "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x70C004477",
        "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.READS_TO_CORE.REMOTE_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x730004477",
        "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x733004477",
        "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.WRITE_ESTIMATE.MEMORY",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0xFBFF80822",
        "PublicDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM) Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data read requests that miss the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0x21",
        "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
        "PublicDescription": "Counts demand data read requests that miss the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Cycles where data return is pending for a Demand Data Read request who miss L3 cache.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
        "PublicDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
        "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.  Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "2000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Number of times an RTM execution aborted.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.ABORTED",
        "PublicDescription": "Counts the number of times RTM abort was triggered. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt)",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.ABORTED_EVENTS",
        "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt). Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.ABORTED_MEM",
        "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts). Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
        "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
        "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Number of times an RTM execution successfully committed",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.COMMIT",
        "PublicDescription": "Counts the number of times RTM commit succeeded. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of times an RTM execution started.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.START",
        "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
        "Counter": "0,1,2,3",
        "EventCode": "0x54",
        "EventName": "TX_MEM.ABORT_CAPACITY_READ",
        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
        "Counter": "0,1,2,3",
        "EventCode": "0x54",
        "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
        "Counter": "0,1,2,3",
        "EventCode": "0x54",
        "EventName": "TX_MEM.ABORT_CONFLICT",
        "PublicDescription": "Counts the number of times a TSX line had a cache conflict. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    }
]
