[
    {
        "BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x51",
        "EventName": "DL1.DIRTY_EVICTION",
        "PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.  Does not count evictions or dirty writebacks caused by snoops.  Does not count a replacement unless a (dirty) line was written back.",
        "SampleAfterValue": "200003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "L1D.HWPF_MISS",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "L1D.HWPF_MISS",
        "PublicDescription": "L1D.HWPF_MISS Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x20",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "L1D.REPLACEMENT",
        "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
        "Counter": "0,1,2,3",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.FB_FULL",
        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EdgeDetect": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
        "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
        "Counter": "0,1,2,3",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.L2_STALLS",
        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of L1D misses that are outstanding",
        "Counter": "0,1,2,3",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING",
        "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles with L1D load Misses outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
        "PublicDescription": "Counts duration of L1D miss outstanding in cycles. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 cache lines filling L2",
        "Counter": "0,1,2,3",
        "EventCode": "0x25",
        "EventName": "L2_LINES_IN.ALL",
        "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1f",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Exclusive state",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x25",
        "EventName": "L2_LINES_IN.E",
        "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Exclusive state. Counts on a per core basis.",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Forward state",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x25",
        "EventName": "L2_LINES_IN.F",
        "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Forward state. Counts on a per core basis.",
        "SampleAfterValue": "1000003",
        "UMask": "0x10",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Modified state",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x25",
        "EventName": "L2_LINES_IN.M",
        "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Modified state. Counts on a per core basis.",
        "SampleAfterValue": "1000003",
        "UMask": "0x8",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Shared state",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x25",
        "EventName": "L2_LINES_IN.S",
        "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Shared state. Counts on a per core basis.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of L2 cache lines that are evicted due to an L2 cache fill",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x26",
        "EventName": "L2_LINES_OUT.NON_SILENT",
        "PublicDescription": "Counts the number of L2 cache lines that are evicted due to an L2 cache fill. Increments on the core that brought the line in originally.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
        "Counter": "0,1,2,3",
        "EventCode": "0x26",
        "EventName": "L2_LINES_OUT.NON_SILENT",
        "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3 Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of L2 cache lines that are silently dropped due to an L2 cache fill",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x26",
        "EventName": "L2_LINES_OUT.SILENT",
        "PublicDescription": "Counts the number of L2 cache lines that are silently dropped due to an L2 cache fill.  Increments on the core that brought the line in originally.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0x26",
        "EventName": "L2_LINES_OUT.SILENT",
        "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache. These lines are typically in Shared or Exclusive state. A non-threaded event. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",
        "Counter": "0,1,2,3",
        "EventCode": "0x26",
        "EventName": "L2_LINES_OUT.USELESS_HWPF",
        "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES]",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.ALL",
        "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES] Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0xff",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of L2 Cache Accesses that resulted in a Hit from a front door request only (does not include rejects or recycles), per core event",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.HIT",
        "SampleAfterValue": "200003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.HIT",
        "PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT] Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0xdf",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of total L2 Cache Accesses that resulted in a Miss from a front door request only (does not include rejects or recycles), per core event",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.MISS",
        "SampleAfterValue": "200003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_RQSTS.MISS]",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.MISS",
        "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS] Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x3f",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of L2 Cache Accesses that miss the L2 and get BBL reject  short and long rejects, per core event",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.REJECTS",
        "SampleAfterValue": "200003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "L2 code requests",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_CODE_RD",
        "PublicDescription": "Counts the total number of L2 code requests. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0xe4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand Data Read access L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
        "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0xe1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand requests that miss L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
        "PublicDescription": "Counts demand requests that miss L2 cache. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x27",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand requests to L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
        "PublicDescription": "Counts demand requests to L2 cache. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0xe7",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2_RQSTS.ALL_HWPF",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_HWPF",
        "PublicDescription": "L2_RQSTS.ALL_HWPF Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0xf0",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "RFO requests to L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_RFO",
        "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0xe2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.CODE_RD_HIT",
        "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0xc4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 cache misses when fetching instructions",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.CODE_RD_MISS",
        "PublicDescription": "Counts L2 cache misses when fetching instructions. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x24",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand Data Read requests that hit L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
        "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0xc1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand Data Read miss L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
        "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x21",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.HIT",
        "PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT] Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0xdf",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2_RQSTS.HWPF_MISS",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.HWPF_MISS",
        "PublicDescription": "L2_RQSTS.HWPF_MISS Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x30",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_REQUEST.MISS]",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.MISS",
        "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS] Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x3f",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "All accesses to L2 cache [This event is alias to L2_REQUEST.ALL]",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.REFERENCES",
        "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL] Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0xff",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "RFO requests that hit L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.RFO_HIT",
        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0xc2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "RFO requests that miss L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.RFO_MISS",
        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x22",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "SW prefetch requests that hit L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.SWPF_HIT",
        "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0xc8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "SW prefetch requests that miss L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.SWPF_MISS",
        "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x28",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 writebacks that access L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x23",
        "EventName": "L2_TRANS.L2_WB",
        "PublicDescription": "Counts L2 writebacks that access L2 cache. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x40",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles when L1D is locked",
        "Counter": "0,1,2,3",
        "EventCode": "0x42",
        "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
        "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION). Available PDIST counters: 0",
        "SampleAfterValue": "2000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x2e",
        "EventName": "LONGEST_LAT_CACHE.MISS",
        "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
        "SampleAfterValue": "200003",
        "UMask": "0x41",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x2e",
        "EventName": "LONGEST_LAT_CACHE.MISS",
        "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x41",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x2e",
        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
        "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
        "SampleAfterValue": "200003",
        "UMask": "0x4f",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x2e",
        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
        "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x4f",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x35",
        "EventName": "MEM_BOUND_STALLS_IFETCH.ALL",
        "SampleAfterValue": "1000003",
        "UMask": "0x7f",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x35",
        "EventName": "MEM_BOUND_STALLS_IFETCH.L2_HIT",
        "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which missed in the L2 cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x35",
        "EventName": "MEM_BOUND_STALLS_IFETCH.L2_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x7e",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which hit in the LLC. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x35",
        "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_HIT",
        "SampleAfterValue": "1000003",
        "UMask": "0x6",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x35",
        "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x78",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS_LOAD.ALL",
        "SampleAfterValue": "1000003",
        "UMask": "0x7f",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS_LOAD.L2_HIT",
        "PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which missed in the L2 cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS_LOAD.L2_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x7e",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT",
        "SampleAfterValue": "1000003",
        "UMask": "0x6",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x78",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a store buffer full condition",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS_LOAD.SBFULL",
        "SampleAfterValue": "1000003",
        "UMask": "0x80",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Retired load instructions.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.ALL_LOADS",
        "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x81",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired store instructions.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.ALL_STORES",
        "PublicDescription": "Counts all retired store instructions. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x82",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "All retired memory instructions.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.ANY",
        "PublicDescription": "Counts all retired memory instructions - loads and stores. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x83",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions with locked access.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
        "PublicDescription": "Counts retired load instructions with locked access. Available PDIST counters: 0",
        "SampleAfterValue": "100007",
        "UMask": "0x21",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
        "PublicDescription": "Counts retired load instructions that split across a cacheline boundary. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x41",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
        "PublicDescription": "Counts retired store instructions that split across a cacheline boundary. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x42",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions that hit the STLB.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.STLB_HIT_LOADS",
        "PublicDescription": "Number of retired load instructions with a clean hit in the 2nd-level TLB (STLB). Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x9",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired store instructions that hit the STLB.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.STLB_HIT_STORES",
        "PublicDescription": "Number of retired store instructions that hit in the 2nd-level TLB (STLB). Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0xa",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions that miss the STLB.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
        "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x11",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired store instructions that miss the STLB.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
        "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x12",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Completed demand load uops that miss the L1 d-cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0x43",
        "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY",
        "PublicDescription": "Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss) Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0xfd",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
        "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3. Available PDIST counters: 0",
        "SampleAfterValue": "20011",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
        "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache. Available PDIST counters: 0",
        "SampleAfterValue": "20011",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
        "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
        "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache. Available PDIST counters: 0",
        "SampleAfterValue": "20011",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd3",
        "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
        "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100007",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd4",
        "EventName": "MEM_LOAD_MISC_RETIRED.UC",
        "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock). Available PDIST counters: 0",
        "SampleAfterValue": "100007",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.FB_HIT",
        "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. Available PDIST counters: 0",
        "SampleAfterValue": "100007",
        "UMask": "0x40",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L1_HIT",
        "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions missed L1 cache as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L1_MISS",
        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L2_HIT",
        "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions missed L2 cache as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L2_MISS",
        "PublicDescription": "Counts retired load instructions missed L2 cache as data sources. Available PDIST counters: 0",
        "SampleAfterValue": "100021",
        "UMask": "0x10",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L3_HIT",
        "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100021",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions missed L3 cache as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L3_MISS",
        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "50021",
        "UMask": "0x20",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of load ops retired that miss the L3 cache and hit in DRAM",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xd4",
        "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.LOCAL_DRAM",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load ops retired that hit the L1 data cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
        "SampleAfterValue": "200003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load ops retired that miss in the L1 data cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
        "SampleAfterValue": "200003",
        "UMask": "0x40",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load ops retired that hit in the L2 cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
        "SampleAfterValue": "200003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load ops retired that miss in the L2 cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
        "SampleAfterValue": "200003",
        "UMask": "0x80",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
        "SampleAfterValue": "200003",
        "UMask": "0x1c",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT",
        "SampleAfterValue": "200003",
        "UMask": "0x20",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons:  load buffer, store buffer or RSV full.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x04",
        "EventName": "MEM_SCHEDULER_BLOCK.ALL",
        "SampleAfterValue": "20003",
        "UMask": "0x7",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x04",
        "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF",
        "SampleAfterValue": "20003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x04",
        "EventName": "MEM_SCHEDULER_BLOCK.RSV",
        "SampleAfterValue": "20003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x04",
        "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF",
        "SampleAfterValue": "20003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "MEM_STORE_RETIRED.L2_HIT",
        "Counter": "0,1,2,3",
        "EventCode": "0x44",
        "EventName": "MEM_STORE_RETIRED.L2_HIT",
        "PublicDescription": "MEM_STORE_RETIRED.L2_HIT Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of load ops retired.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
        "SampleAfterValue": "200003",
        "UMask": "0x81",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of store ops retired.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
        "SampleAfterValue": "200003",
        "UMask": "0x82",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
        "Counter": "0,1",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x400",
        "SampleAfterValue": "1000003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
        "Counter": "0,1",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x80",
        "SampleAfterValue": "1000003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
        "Counter": "0,1",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x10",
        "SampleAfterValue": "1000003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
        "Counter": "0,1",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x800",
        "SampleAfterValue": "1000003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
        "Counter": "0,1",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x100",
        "SampleAfterValue": "1000003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
        "Counter": "0,1",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x20",
        "SampleAfterValue": "1000003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
        "Counter": "0,1",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x4",
        "SampleAfterValue": "1000003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
        "Counter": "0,1",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x200",
        "SampleAfterValue": "1000003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
        "Counter": "0,1",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x40",
        "SampleAfterValue": "1000003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
        "Counter": "0,1",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x8",
        "SampleAfterValue": "1000003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load uops retired that performed one or more locks",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
        "SampleAfterValue": "200003",
        "UMask": "0x21",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of memory uops retired that were splits.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.SPLIT",
        "SampleAfterValue": "200003",
        "UMask": "0x43",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of retired split load uops.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
        "SampleAfterValue": "200003",
        "UMask": "0x41",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of retired split store uops.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
        "SampleAfterValue": "200003",
        "UMask": "0x42",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of memory uops retired that missed in the second level TLB.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.STLB_MISS",
        "SampleAfterValue": "200003",
        "UMask": "0x13",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load uops retired that miss in the second Level TLB.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
        "SampleAfterValue": "200003",
        "UMask": "0x11",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of store uops retired that miss in the second level TLB.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
        "SampleAfterValue": "200003",
        "UMask": "0x12",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
        "SampleAfterValue": "1000003",
        "UMask": "0x6",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Retired memory uops for any access",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xe5",
        "EventName": "MEM_UOP_RETIRED.ANY",
        "PublicDescription": "Number of retired micro-operations (uops) for load or store memory accesses Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x3",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10004",
        "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3F803C0004",
        "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10003C0004",
        "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x4003C0004",
        "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x8003C0004",
        "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand data reads that have any type of response.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10001",
        "PublicDescription": "Counts demand data reads that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand data reads that have any type of response.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10001",
        "PublicDescription": "Counts demand data reads that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by the L3 cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3F803C0001",
        "PublicDescription": "Counts demand data reads that were supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10003C0001",
        "PublicDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10003C0001",
        "PublicDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x4003C0001",
        "PublicDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x8003C0001",
        "PublicDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches which forwarded the unmodified data to the requesting core.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x8003C0001",
        "PublicDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches which forwarded the unmodified data to the requesting core. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10002",
        "PublicDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10002",
        "PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_RFO.L3_HIT",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3F803C0002",
        "PublicDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10003C0002",
        "PublicDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10003C0002",
        "PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Any memory transaction that reached the SQ.",
        "Counter": "0,1,2,3",
        "EventCode": "0x21",
        "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
        "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc.. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x80",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand and prefetch data reads",
        "Counter": "0,1,2,3",
        "EventCode": "0x21",
        "EventName": "OFFCORE_REQUESTS.DATA_RD",
        "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cacheable and Non-Cacheable code read requests",
        "Counter": "0,1,2,3",
        "EventCode": "0x21",
        "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
        "PublicDescription": "Counts both cacheable and Non-Cacheable code read requests. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand Data Read requests sent to uncore",
        "Counter": "0,1,2,3",
        "EventCode": "0x21",
        "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
        "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
        "Counter": "0,1,2,3",
        "EventCode": "0x21",
        "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
        "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
        "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
        "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles where at least 1 outstanding demand data read request is pending.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
        "PublicDescription": "Cycles where at least 1 outstanding demand data read request is pending. Available PDIST counters: 0",
        "SampleAfterValue": "2000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
        "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
        "Counter": "0,1,2,3",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
        "PublicDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
        "Counter": "0,1,2,3",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
        "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
        "Counter": "0,1,2,3",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
        "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.   Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.",
        "Counter": "0,1,2,3",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
        "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2c",
        "EventName": "SQ_MISC.BUS_LOCK",
        "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically.  Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x10",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.",
        "Counter": "0,1,2,3",
        "EventCode": "0x40",
        "EventName": "SW_PREFETCH_ACCESS.ANY",
        "PublicDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0xf",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of PREFETCHNTA instructions executed.",
        "Counter": "0,1,2,3",
        "EventCode": "0x40",
        "EventName": "SW_PREFETCH_ACCESS.NTA",
        "PublicDescription": "Counts the number of PREFETCHNTA instructions executed. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of PREFETCHW instructions executed.",
        "Counter": "0,1,2,3",
        "EventCode": "0x40",
        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
        "PublicDescription": "Counts the number of PREFETCHW instructions executed. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of PREFETCHT0 instructions executed.",
        "Counter": "0,1,2,3",
        "EventCode": "0x40",
        "EventName": "SW_PREFETCH_ACCESS.T0",
        "PublicDescription": "Counts the number of PREFETCHT0 instructions executed. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
        "Counter": "0,1,2,3",
        "EventCode": "0x40",
        "EventName": "SW_PREFETCH_ACCESS.T1_T2",
        "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x71",
        "EventName": "TOPDOWN_FE_BOUND.ICACHE",
        "SampleAfterValue": "1000003",
        "UMask": "0x20",
        "Unit": "cpu_atom"
    }
]
