[
    {
        "BriefDescription": "Requests rejected by the L2Q",
        "Counter": "0,1,2,3",
        "EventCode": "0x31",
        "EventName": "CORE_REJECT_L2Q.ALL",
        "PublicDescription": "Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops.",
        "SampleAfterValue": "200003"
    },
    {
        "BriefDescription": "L1 Cache evictions for dirty data",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "DL1.REPLACEMENT",
        "PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory.  No count will occur if the evicted line is clean, and hence does not require a writeback.",
        "SampleAfterValue": "200003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
        "Counter": "0,1,2,3",
        "EventCode": "0x86",
        "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
        "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss.  Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Requests rejected by the XQ",
        "Counter": "0,1,2,3",
        "EventCode": "0x30",
        "EventName": "L2_REJECT_XQ.ALL",
        "PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims.",
        "SampleAfterValue": "200003"
    },
    {
        "BriefDescription": "L2 cache request misses",
        "Counter": "0,1,2,3",
        "EventCode": "0x2E",
        "EventName": "LONGEST_LAT_CACHE.MISS",
        "PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x41"
    },
    {
        "BriefDescription": "L2 cache requests",
        "Counter": "0,1,2,3",
        "EventCode": "0x2E",
        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
        "PublicDescription": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x4f"
    },
    {
        "BriefDescription": "Loads retired that came from DRAM (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
        "PEBS": "2",
        "PublicDescription": "Counts memory load uops retired where the data is retrieved from DRAM.  Event is counted at retirement, so the speculative loads are ignored.  A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.",
        "SampleAfterValue": "200003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.HITM",
        "PEBS": "2",
        "PublicDescription": "Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM).  More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data.  Loads that obtain a HITM response incur greater latency than most is typical for a load.  In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value.  This event is useful for locating sharing, false sharing, and contended locks.",
        "SampleAfterValue": "200003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
        "PEBS": "2",
        "PublicDescription": "Counts load uops retired that hit the L1 data cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
        "PEBS": "2",
        "PublicDescription": "Counts load uops retired that miss the L1 data cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
        "PEBS": "2",
        "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
        "PEBS": "2",
        "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Loads retired that hit WCB (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT",
        "PEBS": "2",
        "PublicDescription": "Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache.  Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache.  If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data.  When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs.",
        "SampleAfterValue": "200003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Memory uops retired (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD0",
        "EventName": "MEM_UOPS_RETIRED.ALL",
        "PEBS": "2",
        "PublicDescription": "Counts the number of memory uops retired that is either a loads or a store or both.",
        "SampleAfterValue": "200003",
        "UMask": "0x83"
    },
    {
        "BriefDescription": "Load uops retired (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD0",
        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
        "PEBS": "2",
        "PublicDescription": "Counts the number of load uops retired.",
        "SampleAfterValue": "200003",
        "UMask": "0x81"
    },
    {
        "BriefDescription": "Store uops retired (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD0",
        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
        "PEBS": "2",
        "PublicDescription": "Counts the number of store uops retired.",
        "SampleAfterValue": "200003",
        "UMask": "0x82"
    },
    {
        "BriefDescription": "Locked load uops retired (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD0",
        "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
        "PEBS": "2",
        "PublicDescription": "Counts locked memory uops retired.  This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.)  A locked access is one with a lock prefix, or an exchange to memory.  See the SDM for a complete description of which memory load accesses are locks.",
        "SampleAfterValue": "200003",
        "UMask": "0x21"
    },
    {
        "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD0",
        "EventName": "MEM_UOPS_RETIRED.SPLIT",
        "PEBS": "2",
        "PublicDescription": "Counts memory uops retired where the data requested spans a 64 byte cache line boundary.",
        "SampleAfterValue": "200003",
        "UMask": "0x43"
    },
    {
        "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD0",
        "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
        "PEBS": "2",
        "PublicDescription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.",
        "SampleAfterValue": "200003",
        "UMask": "0x41"
    },
    {
        "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD0",
        "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
        "PEBS": "2",
        "PublicDescription": "Counts store uops retired where the data requested spans a 64 byte cache line boundary.",
        "SampleAfterValue": "200003",
        "UMask": "0x42"
    },
    {
        "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000013091",
        "PublicDescription": "Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data reads (demand & prefetch) hit the L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000043091",
        "PublicDescription": "Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x1000003091",
        "PublicDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0200003091",
        "PublicDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x4000003091",
        "PublicDescription": "Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000013010",
        "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000043010",
        "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x1000003010",
        "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0200003010",
        "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x4000003010",
        "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x00000132b7",
        "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x00000432b7",
        "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x10000032b7",
        "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x02000032b7",
        "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x40000032b7",
        "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000018000",
        "PublicDescription": "Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts requests to the uncore subsystem hit the L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000048000",
        "PublicDescription": "Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x1000008000",
        "PublicDescription": "Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0200008000",
        "PublicDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x4000008000",
        "PublicDescription": "Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000010022",
        "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000040022",
        "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x1000000022",
        "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0200000022",
        "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x4000000022",
        "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts bus lock and split lock requests have any transaction responses from the uncore subsystem.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000010400",
        "PublicDescription": "Counts bus lock and split lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts bus lock and split lock requests hit the L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000040400",
        "PublicDescription": "Counts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x1000000400",
        "PublicDescription": "Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0200000400",
        "PublicDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x4000000400",
        "PublicDescription": "Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000010008",
        "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000040008",
        "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x1000000008",
        "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0200000008",
        "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.COREWB.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x4000000008",
        "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000010004",
        "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000040004",
        "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x1000000004",
        "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0200000004",
        "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x4000000004",
        "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000010001",
        "PublicDescription": "Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000040001",
        "PublicDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x1000000001",
        "PublicDescription": "Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0200000001",
        "PublicDescription": "Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x4000000001",
        "PublicDescription": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000010002",
        "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000040002",
        "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x1000000002",
        "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0200000002",
        "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x4000000002",
        "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000010800",
        "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000040800",
        "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x1000000800",
        "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0200000800",
        "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x4000000800",
        "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000012000",
        "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000042000",
        "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x1000002000",
        "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0200002000",
        "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x4000002000",
        "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000010010",
        "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000040010",
        "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x1000000010",
        "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0200000010",
        "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x4000000010",
        "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000010020",
        "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000040020",
        "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x1000000020",
        "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0200000020",
        "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x4000000020",
        "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  have any transaction responses from the uncore subsystem.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000014800",
        "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  hit the L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000044800",
        "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x1000004800",
        "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  true miss for the L2 cache with a snoop miss in the other processor module.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0200004800",
        "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  outstanding, per cycle, from the time of the L2 miss to when any response is received.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x4000004800",
        "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.ANY_RESPONSE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000011000",
        "PublicDescription": "Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data cache lines requests by software prefetch instructions hit the L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0000041000",
        "PublicDescription": "Counts data cache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x1000001000",
        "PublicDescription": "Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
        "MSRIndex": "0x1a6, 0x1a7",
        "MSRValue": "0x0200001000",
        "PublicDescription": "Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7",
        "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x4000001000",
        "PublicDescription": "Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    }
]
