[
  {
    "EventCode": "0x10066",
    "EventName": "PM_ADJUNCT_CYC",
    "BriefDescription": "Cycles in which the thread is in Adjunct state. MSR[S HV PR] bits = 011."
  },
  {
    "EventCode": "0x2E010",
    "EventName": "PM_ADJUNCT_INST_CMPL",
    "BriefDescription": "PowerPC instruction completed while the thread was in Adjunct state."
  },
  {
    "EventCode": "0x200F2",
    "EventName": "PM_INST_DISP",
    "BriefDescription": "PowerPC instruction dispatched."
  },
  {
    "EventCode": "0x300F6",
    "EventName": "PM_LD_DEMAND_MISS_L1",
    "BriefDescription": "The L1 cache was reloaded with a line that fulfills a demand miss request. Counted at reload time, before finish."
  },
  {
    "EventCode": "0x40012",
    "EventName": "PM_L1_ICACHE_RELOADED_ALL",
    "BriefDescription": "Counts all instruction cache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch."
  },
  {
    "EventCode": "0x00000038BC",
    "EventName": "PM_ISYNC_CMPL",
    "BriefDescription": "Isync completion count per thread."
  },
  {
    "EventCode": "0x000000C088",
    "EventName": "PM_LD0_32B_FIN",
    "BriefDescription": "256-bit load finished in the LD0 load execution unit."
  },
  {
    "EventCode": "0x000000C888",
    "EventName": "PM_LD1_32B_FIN",
    "BriefDescription": "256-bit load finished in the LD1 load execution unit."
  },
  {
    "EventCode": "0x000000C090",
    "EventName": "PM_LD0_UNALIGNED_FIN",
    "BriefDescription": "Load instructions in LD0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time."
  },
  {
    "EventCode": "0x000000C890",
    "EventName": "PM_LD1_UNALIGNED_FIN",
    "BriefDescription": "Load instructions in LD1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time."
  },
  {
    "EventCode": "0x000000C0A4",
    "EventName": "PM_ST0_UNALIGNED_FIN",
    "BriefDescription": "Store instructions in ST0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time."
  },
  {
    "EventCode": "0x000000C8A4",
    "EventName": "PM_ST1_UNALIGNED_FIN",
    "BriefDescription": "Store instructions in ST1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time."
  },
  {
    "EventCode": "0x000000D0B4",
    "EventName": "PM_DC_PREF_STRIDED_CONF",
    "BriefDescription": "A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software."
  },
  {
    "EventCode": "0x0000004884",
    "EventName": "PM_NO_FETCH_IBUF_FULL_CYC",
    "BriefDescription": "Cycles in which no instructions are fetched because there is no room in the instruction buffers."
  }
]
