[
    {
        "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "6",
        "EventCode": "0xa3",
        "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x6"
    },
    {
        "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc3",
        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
        "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x80",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "1009",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x10",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "20011",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x100",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "503",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x20",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x4",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x200",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "101",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x40",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "2003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x8",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "50021",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_CODE_RD.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x73C000004",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FBFC00004",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3F84400004",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x104000004",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x708000004",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_DATA_RD.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x73C000001",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FBFC00001",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3F84400001",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x104000001",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x730000001",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x708000001",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_RFO.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x73C000002",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_RFO.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3F3FC00002",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3F04400002",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x104000002",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_RFO.SNC_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x708000002",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x73C000400",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FBFC00400",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3F84400400",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x104000400",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L3.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x94002380",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L3.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x84002380",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.ITOM.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x84000002",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.OTHER.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FBFC08000",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.OTHER.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3F84408000",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.PREFETCHES.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3F844027F0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.READS_TO_CORE.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x73C000477",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.READS_TO_CORE.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3F3FC00477",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3F04400477",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x70CC00477",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x104000477",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x70C000477",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.READS_TO_CORE.REMOTE_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x730000477",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x731800477",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.READS_TO_CORE.SNC_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x708000477",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.STREAMING_WR.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x94000800",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x84000800",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.WRITE_ESTIMATE.MEMORY",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0xFBFF80822",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data read requests that miss the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xb0",
        "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
        "SampleAfterValue": "100003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
        "PublicDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.  Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
        "SampleAfterValue": "1000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "This event is deprecated.",
        "Counter": "0,1,2,3",
        "Deprecated": "1",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
        "SampleAfterValue": "2000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.",
        "Counter": "0,1,2,3",
        "CounterMask": "6",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
        "PublicDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.  Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
        "SampleAfterValue": "2000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Number of times an RTM execution aborted.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.ABORTED",
        "PublicDescription": "Counts the number of times RTM abort was triggered.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt)",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.ABORTED_EVENTS",
        "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt).",
        "SampleAfterValue": "100003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.ABORTED_MEM",
        "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
        "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
        "SampleAfterValue": "100003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
        "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
        "SampleAfterValue": "100003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Number of times an RTM execution successfully committed",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.COMMIT",
        "PublicDescription": "Counts the number of times RTM commit succeeded.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of times an RTM execution started.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.START",
        "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x5d",
        "EventName": "TX_EXEC.MISC2",
        "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x5d",
        "EventName": "TX_EXEC.MISC3",
        "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
        "Counter": "0,1,2,3",
        "EventCode": "0x54",
        "EventName": "TX_MEM.ABORT_CAPACITY_READ",
        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
        "SampleAfterValue": "100003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
        "Counter": "0,1,2,3",
        "EventCode": "0x54",
        "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
        "Counter": "0,1,2,3",
        "EventCode": "0x54",
        "EventName": "TX_MEM.ABORT_CONFLICT",
        "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    }
]
