[
    {
        "BriefDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0xc1",
        "EventName": "ASSISTS.HARDWARE",
        "PublicDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events.  This includes, but not limited to, assists at EXE or MEM uop writeback like AVX* load/store/gather/scatter (non-FP GSSE-assist ) , assists generated by ROB like PEBS and RTIT, Uncore trap, RAR (Remote Action Request) and CET (Control flow Enforcement Technology) assists.",
        "SampleAfterValue": "100003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "ASSISTS.PAGE_FAULT",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0xc1",
        "EventName": "ASSISTS.PAGE_FAULT",
        "SampleAfterValue": "1000003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to a lock In Progress issued by another core",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x63",
        "EventName": "BUS_LOCK.BLOCKED_CYCLES",
        "PublicDescription": "Counts the number of unhalted cycles a Core is blocked due to a lock In Progress issued by another core. Counts on a per core basis.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to an Accepted lock it issued, includes both split and non-split lock cycles.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x63",
        "EventName": "BUS_LOCK.LOCK_CYCLES",
        "PublicDescription": "Counts the number of unhalted cycles a Core is blocked due to an Accepted lock it issued, includes both split and non-split lock cycles. Counts on a per core basis.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of non-split locks such as UC locks issued by a Core (does not include cache locks)",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x63",
        "EventName": "BUS_LOCK.NON_SPLIT_LOCKS",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of split locks issued by a Core",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x63",
        "EventName": "BUS_LOCK.SPLIT_LOCKS",
        "SampleAfterValue": "1000003",
        "UMask": "0x8",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the L2 Prefetchers are at throttle level 0",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x32",
        "EventName": "DYNAMIC_PREFETCH_THROTTLER.LEVEL0_SOC",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the L2 Prefetcher throttle level is at 1",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x32",
        "EventName": "DYNAMIC_PREFETCH_THROTTLER.LEVEL1_SOC",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the L2 Prefetcher throttle level is at 2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x32",
        "EventName": "DYNAMIC_PREFETCH_THROTTLER.LEVEL2_SOC",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the L2 Prefetcher throttle level is at 3",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x32",
        "EventName": "DYNAMIC_PREFETCH_THROTTLER.LEVEL3_SOC",
        "SampleAfterValue": "1000003",
        "UMask": "0x8",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the L2 Prefetcher throttle level is at 4",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x32",
        "EventName": "DYNAMIC_PREFETCH_THROTTLER.LEVEL4_SOC",
        "SampleAfterValue": "1000003",
        "UMask": "0x10",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts all requests that have any type of response.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.ALL_REQUESTS.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0xFF0000001DFFF",
        "PublicDescription": "Counts all requests that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts full streaming stores (64 bytes, WCiLF) that have any type of response.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x800000010000",
        "PublicDescription": "Counts full streaming stores (64 bytes, WCiLF) that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts partial streaming stores (less than 64 bytes, WCiL) that have any type of response.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x400000010000",
        "PublicDescription": "Counts partial streaming stores (less than 64 bytes, WCiL) that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts streaming stores that have any type of response.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10800",
        "PublicDescription": "Counts streaming stores that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts streaming stores that have any type of response.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10800",
        "PublicDescription": "Counts streaming stores that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles the uncore cannot take further requests",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "CounterMask": "1",
        "EventCode": "0x2d",
        "EventName": "XQ.FULL",
        "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of prefetch requests that were promoted in the XQ to a demand request.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xf4",
        "EventName": "XQ_PROMOTION.ALL",
        "SampleAfterValue": "1000003",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of prefetch requests that were promoted in the XQ to a demand code read.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xf4",
        "EventName": "XQ_PROMOTION.CRDS",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of prefetch requests that were promoted in the XQ to a demand read.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xf4",
        "EventName": "XQ_PROMOTION.DRDS",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of prefetch requests that were promoted in the XQ to a demand RFO.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xf4",
        "EventName": "XQ_PROMOTION.RFOS",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    }
]
