[
    {
        "BriefDescription": "Counts the number of page walks initiated by a demand load that missed the first and second level TLBs.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.MISS_CAUSED_WALK",
        "SampleAfterValue": "200003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts walks that miss the PDE_CACHE",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
        "SampleAfterValue": "200003",
        "UMask": "0x80",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
        "SampleAfterValue": "200003",
        "UMask": "0x20",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
        "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
        "SampleAfterValue": "100003",
        "UMask": "0x320",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "CounterMask": "1",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
        "SampleAfterValue": "100003",
        "UMask": "0x10",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
        "SampleAfterValue": "200003",
        "UMask": "0xe",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0xe",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
        "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
        "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
        "SampleAfterValue": "200003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
        "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
        "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
        "SampleAfterValue": "200003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
        "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
        "PublicDescription": "Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.  A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
        "SampleAfterValue": "200003",
        "UMask": "0x10",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
        "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
        "SampleAfterValue": "100003",
        "UMask": "0x10",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of page walks initiated by a store that missed the first and second level TLBs.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.MISS_CAUSED_WALK",
        "SampleAfterValue": "2000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts walks that miss the PDE_CACHE",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
        "SampleAfterValue": "2000003",
        "UMask": "0x80",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.STLB_HIT",
        "PublicDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.",
        "SampleAfterValue": "2000003",
        "UMask": "0x20",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x13",
        "EventName": "DTLB_STORE_MISSES.STLB_HIT",
        "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
        "SampleAfterValue": "100003",
        "UMask": "0x320",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "CounterMask": "1",
        "EventCode": "0x13",
        "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
        "SampleAfterValue": "100003",
        "UMask": "0x10",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size.  Includes page walks that page fault.",
        "SampleAfterValue": "2000003",
        "UMask": "0xe",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x13",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0xe",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x13",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
        "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
        "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages.  Includes page walks that page fault.",
        "SampleAfterValue": "2000003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x13",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
        "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
        "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages.  Includes page walks that page fault.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x13",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
        "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
        "PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
        "SampleAfterValue": "200003",
        "UMask": "0x10",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x13",
        "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
        "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
        "SampleAfterValue": "100003",
        "UMask": "0x10",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x81",
        "EventName": "ITLB.FILLS",
        "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and a new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
        "SampleAfterValue": "200003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.MISS_CAUSED_WALK",
        "SampleAfterValue": "2000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts walks that miss the PDE_CACHE",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.PDE_CACHE_MISS",
        "SampleAfterValue": "2000003",
        "UMask": "0x80",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.STLB_HIT",
        "SampleAfterValue": "2000003",
        "UMask": "0x20",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x11",
        "EventName": "ITLB_MISSES.STLB_HIT",
        "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
        "SampleAfterValue": "100003",
        "UMask": "0x120",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "CounterMask": "1",
        "EventCode": "0x11",
        "EventName": "ITLB_MISSES.WALK_ACTIVE",
        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
        "SampleAfterValue": "100003",
        "UMask": "0x10",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size.  Includes page walks that page fault.",
        "SampleAfterValue": "2000003",
        "UMask": "0xe",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x11",
        "EventName": "ITLB_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0xe",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
        "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages.  Includes page walks that page fault.",
        "SampleAfterValue": "2000003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x11",
        "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
        "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
        "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages.  Includes page walks that page fault.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x11",
        "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
        "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of page walks outstanding for iside in PMH every cycle.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.WALK_PENDING",
        "PublicDescription": "Counts the number of page walks outstanding for iside in PMH every cycle.  A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.  Walks could be counted by edge detecting on this event, but would count restarted suspended walks.",
        "SampleAfterValue": "200003",
        "UMask": "0x10",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x11",
        "EventName": "ITLB_MISSES.WALK_PENDING",
        "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
        "SampleAfterValue": "100003",
        "UMask": "0x10",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of occurrences a load gets blocked because of a micro TLB miss",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x03",
        "EventName": "LD_BLOCKS.DTLB_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x8",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DTLB miss",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x05",
        "EventName": "LD_HEAD.DTLB_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x10",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x05",
        "EventName": "LD_HEAD.DTLB_MISS_AT_RET",
        "SampleAfterValue": "1000003",
        "UMask": "0x90",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of PMH walks that hit in the L1 or WCBs",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xbc",
        "EventName": "PAGE_WALKER_LOADS.DTLB_L1_HIT",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of PMH walks that hit in the L2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xbc",
        "EventName": "PAGE_WALKER_LOADS.DTLB_L2_HIT",
        "PublicDescription": "Counts the number of PMH walks that hit in the L2.  Includes L2 Hit resulting from and L1D eviction of another core in the same module which is longer latency than a typical L2 hit.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Count number of any STLB flush attempts (Entire, PCID, InvPage, CR3 write, etc)",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xbd",
        "EventName": "TLB_FLUSHES.STLB_ANY",
        "SampleAfterValue": "20003",
        "UMask": "0x20",
        "Unit": "cpu_atom"
    }
]
