[
    {
        "ArchStdEvent": "SW_INCR"
    },
    {
        "ArchStdEvent": "LD_RETIRED"
    },
    {
        "ArchStdEvent": "ST_RETIRED"
    },
    {
        "ArchStdEvent": "INST_RETIRED"
    },
    {
        "ArchStdEvent": "EXC_RETURN"
    },
    {
        "ArchStdEvent": "CID_WRITE_RETIRED"
    },
    {
        "ArchStdEvent": "PC_WRITE_RETIRED"
    },
    {
        "ArchStdEvent": "BR_IMMED_RETIRED"
    },
    {
        "ArchStdEvent": "BR_RETURN_RETIRED"
    },
    {
        "ArchStdEvent": "INST_SPEC"
    },
    {
        "ArchStdEvent": "TTBR_WRITE_RETIRED"
    },
    {
        "ArchStdEvent": "BR_RETIRED"
    },
    {
        "ArchStdEvent": "BR_MIS_PRED_RETIRED"
    },
    {
        "ArchStdEvent": "LD_SPEC"
    },
    {
        "ArchStdEvent": "ST_SPEC"
    },
    {
        "ArchStdEvent": "LDST_SPEC"
    },
    {
        "ArchStdEvent": "DP_SPEC"
    },
    {
        "ArchStdEvent": "ASE_SPEC"
    },
    {
        "ArchStdEvent": "VFP_SPEC"
    },
    {
        "ArchStdEvent": "CRYPTO_SPEC"
    },
    {
        "ArchStdEvent": "ISB_SPEC"
    },
    {
        "PublicDescription": "Instruction retired, conditional branch",
        "EventCode": "0xE8",
        "EventName": "DPU_BR_COND_RETIRED",
        "BriefDescription": "Instruction retired, conditional branch"
    }
]
