[
    {
        "ArchStdEvent": "STALL_FRONTEND",
        "PublicDescription": "Counts cycles when frontend could not send any micro-operations to the rename stage because of frontend resource stalls caused by fetch memory latency or branch prediction flow stalls. STALL_FRONTEND_SLOTS counts SLOTS during the cycle when this event counts."
    },
    {
        "ArchStdEvent": "STALL_BACKEND",
        "PublicDescription": "Counts cycles whenever the rename unit is unable to send any micro-operations to the backend of the pipeline because of backend resource constraints. Backend resource constraints can include issue stage fullness, execution stage fullness, or other internal pipeline resource fullness. All the backend slots were empty during the cycle when this event counts."
    },
    {
        "ArchStdEvent": "STALL",
        "PublicDescription": "Counts cycles when no operations are sent to the rename unit from the frontend or from the rename unit to the backend for any reason (either frontend or backend stall). This event is the sum of STALL_FRONTEND and STALL_BACKEND"
    },
    {
        "ArchStdEvent": "STALL_SLOT_BACKEND",
        "PublicDescription": "Counts slots per cycle in which no operations are sent from the rename unit to the backend due to backend resource constraints. STALL_BACKEND counts during the cycle when STALL_SLOT_BACKEND counts at least 1."
    },
    {
        "ArchStdEvent": "STALL_SLOT_FRONTEND",
        "PublicDescription": "Counts slots per cycle in which no operations are sent to the rename unit from the frontend due to frontend resource constraints."
    },
    {
        "ArchStdEvent": "STALL_SLOT",
        "PublicDescription": "Counts slots per cycle in which no operations are sent to the rename unit from the frontend or from the rename unit to the backend for any reason (either frontend or backend stall). STALL_SLOT is the sum of STALL_SLOT_FRONTEND and STALL_SLOT_BACKEND."
    },
    {
        "PublicDescription": "Counts cycles counted by STALL_BACKEND_BUSY when the backend could not accept any micro-operations\nbecause the simple integer issue queues are full to take any operations for execution.",
        "EventCode": "0x15C",
        "EventName": "DISPATCH_STALL_IQ_SX",
        "BriefDescription": "Dispatch stalled due to IQ full,SX"
    },
    {
        "PublicDescription": "Counts cycles counted by STALL_BACKEND_BUSY when the backend could not accept any micro-operations\nbecause the complex integer issue queues are full and can not take any operations for execution.",
        "EventCode": "0x15D",
        "EventName": "DISPATCH_STALL_IQ_MX",
        "BriefDescription": "Dispatch stalled due to IQ full,MX"
    },
    {
        "PublicDescription": "Counts cycles when the backend could not accept any micro-operations\nbecause the load/store issue queues are full and can not take any operations for execution.",
        "EventCode": "0x15E",
        "EventName": "DISPATCH_STALL_IQ_LS",
        "BriefDescription": "Dispatch stalled due to IQ full,LS"
    },
    {
        "PublicDescription": "Counts cycles counted by STALL_BACKEND_BUSY when the backend could not accept any micro-operations\nbecause the vector issue queues are full and can not take any operations for execution.",
        "EventCode": "0x15F",
        "EventName": "DISPATCH_STALL_IQ_VX",
        "BriefDescription": "Dispatch stalled due to IQ full,VX"
    },
    {
        "PublicDescription": "Counts cycles counted by STALL_BACKEND_BUSY when the backend could not accept any micro-operations\nbecause the commit queue is full and can not take any operations for execution.",
        "EventCode": "0x160",
        "EventName": "DISPATCH_STALL_MCQ",
        "BriefDescription": "Dispatch stalled due to MCQ full"
    },
    {
        "ArchStdEvent": "STALL_BACKEND_MEM",
        "PublicDescription": "Counts cycles when the backend is stalled because there is a pending demand load request in progress in the last level core cache."
    },
    {
        "ArchStdEvent": "STALL_FRONTEND_MEMBOUND",
        "PublicDescription": "Counts cycles when the frontend could not send any micro-operations to the rename stage due to resource constraints in the memory resources."
    },
    {
        "ArchStdEvent": "STALL_FRONTEND_L1I",
        "PublicDescription": "Counts cycles when the frontend is stalled because there is an instruction fetch request pending in the level 1 instruction cache."
    },
    {
        "ArchStdEvent": "STALL_FRONTEND_MEM",
        "PublicDescription": "Counts cycles when the frontend is stalled because there is an instruction fetch request pending in the last level core cache."
    },
    {
        "ArchStdEvent": "STALL_FRONTEND_TLB",
        "PublicDescription": "Counts when the frontend is stalled on any TLB misses being handled. This event also counts the TLB accesses made by hardware prefetches."
    },
    {
        "ArchStdEvent": "STALL_FRONTEND_CPUBOUND",
        "PublicDescription": "Counts cycles when the frontend could not send any micro-operations to the rename stage due to resource constraints in the CPU resources excluding memory resources."
    },
    {
        "ArchStdEvent": "STALL_FRONTEND_FLOW",
        "PublicDescription": "Counts cycles when the frontend could not send any micro-operations to the rename stage due to resource constraints in the branch prediction unit."
    },
    {
        "ArchStdEvent": "STALL_FRONTEND_FLUSH",
        "PublicDescription": "Counts cycles when the frontend could not send any micro-operations to the rename stage as the frontend is recovering from a machine flush or resteer. Example scenarios that cause a flush include branch mispredictions, taken exceptions, micro-architectural flush etc."
    },
    {
        "ArchStdEvent": "STALL_BACKEND_MEMBOUND",
        "PublicDescription": "Counts cycles when the backend could not accept any micro-operations due to resource constraints in the memory resources."
    },
    {
        "ArchStdEvent": "STALL_BACKEND_L1D",
        "PublicDescription": "Counts cycles when the backend is stalled because there is a pending demand load request in progress in the level 1 data cache."
    },
    {
        "ArchStdEvent": "STALL_BACKEND_L2D",
        "PublicDescription": "Counts cycles when the backend is stalled because there is a pending demand load request in progress in the level 2 data cache."
    },
    {
        "ArchStdEvent": "STALL_BACKEND_TLB",
        "PublicDescription": "Counts cycles when the backend is stalled on any demand TLB misses being handled."
    },
    {
        "ArchStdEvent": "STALL_BACKEND_ST",
        "PublicDescription": "Counts cycles when the backend is stalled and there is a store that has not reached the pre-commit stage."
    },
    {
        "ArchStdEvent": "STALL_BACKEND_CPUBOUND",
        "PublicDescription": "Counts cycles when the backend could not accept any micro-operations due to any resource constraints in the CPU excluding memory resources."
    },
    {
        "ArchStdEvent": "STALL_BACKEND_BUSY",
        "PublicDescription": "Counts cycles when the backend could not accept any micro-operations because the issue queues are full to take any operations for execution."
    },
    {
        "ArchStdEvent": "STALL_BACKEND_ILOCK",
        "PublicDescription": "Counts cycles when the backend could not accept any micro-operations due to resource constraints imposed by input dependency."
    },
    {
        "ArchStdEvent": "STALL_BACKEND_RENAME",
        "PublicDescription": "Counts cycles when backend is stalled even when operations are available from the frontend but at least one is not ready to be sent to the backend because no rename register is available."
    }
]
