#
# Copyright 2014, General Dynamics C4 Systems
#
# This software may be distributed and modified according to the terms of
# the GNU General Public License version 2. Note that NO WARRANTY is provided.
# See "LICENSE_GPLv2.txt" for details.
#
# @TAG(GD_GPL)
#

config HAVE_ARCH_TIMER
    bool
    default y
    depends on ARM_CORTEX_A15

config ENABLE_A9_PREFETCHER
    bool "Enable Cortex-A9 prefetcher"
    default n
    depends on ARM_CORTEX_A9
    help
        Cortex-A9 has an L1 and L2 prefetcher. By default
        they are disabled. This config options allows
        them to be turned on. Enabling the prefetchers
        requires that the kernel be in secure mode. ARM
        documents indicate that as of r4p1 version of
        Cortex-A9 the bits used to enable the prefetchers
        no longer exist, it is not clear if this is just
        a document error or not.

config EXPORT_PMU_USER
    bool "PL0 access to PMU"
    default n
    depends on ARCH_ARM_V7A || ARCH_ARM_V8A
    help
        Grant user access to Performance Monitoring Unit.
        WARNING: While useful for evaluating performance,
        this option opens timing and covert channels.

config EXPORT_PCNT_USER
    bool "PL0 access to generic timer CNTPCT and CNTFRQ"
    default y
    depends on HAVE_ARCH_TIMER
    help
        Grant user access to physical counter and counter
        frequency registers of the generic timer.
        WARNING: selecting this option opens a timing
        channel

config EXPORT_VCNT_USER
    bool "PL0 access to generic timer CNTVCT and CNTFRQ"
    default y
    depends on HAVE_ARCH_TIMER
    help
        Grant user access to virtual counter and counter
        frequency registers of the generic timer.
        WARNING: selecting this option opens a timing
        channel

