#
# Copyright 2014, General Dynamics C4 Systems
#
# This software may be distributed and modified according to the terms of
# the GNU General Public License version 2. Note that NO WARRANTY is provided.
# See "LICENSE_GPLv2.txt" for details.
#
# @TAG(GD_GPL)
#

menu "System Interrupt Management"
    choice
        prompt "IRQ Controller"
        depends on PLAT_PC99
        default IRQ_PIC if ARCH_IA32
        default IRQ_IOAPIC if ARCH_X86_64
        help
            Select the IRQ controller seL4 will use. Code for others may
            still be included if needed to disable at run time
        config IRQ_PIC
            bool "PIC"
            help
                Use the legacy PIC controller
        config IRQ_IOAPIC
            bool "IOAPIC"
            help
                Use one or more IOAPIC controllers
    endchoice

    config MAX_NUM_IOAPIC
        prompt "Max supported IOAPICs"
        depends on IRQ_IOAPIC
        int
        default 1
        help
            Configure the maximum number of IOAPIC controllers that can
            be supported. SeL4 will detect IOAPICs regardless of whether
            the IOAPIC will actually be used as the final IRQ controller

    choice
        prompt "Local APIC mode"
        depends on ARCH_X86
        default XAPIC if ARCH_IA32
        default X2APIC if ARCH_X86_64
        help
            Select the mode local APIC will use. Not all machines support
            X2APIC mode.
        config XAPIC
            bool "XAPIC"
            help
                Use XAPIC mode for local APIC
        config X2APIC
            bool "X2APIC"
            help
                Use X2APIC mode for local APIC
    endchoice

    config USE_LOGICAL_IDS
        bool "Use logical IDs for IPIs broadcasting"
        depends on MAX_NUM_NODES != 1
        default n
        help
            Use logical IDs to broadcast IPI between cores. Not all machines
            support logical IDs. In xAPIC mode only 8 cores can be addressed
            using logical IDs.
endmenu

config IOMMU
    bool "IOMMU support"
        depends on PLAT_PC99
        default y
        help
            IOMMU support for VT-d enabled chipset

config VTX
    bool "VTX support"
        depends on PLAT_PC99
        default n
        help
            VTX support

config MAX_VPIDS
    prompt "Max VPIDs to support"
    depends on VTX
    range 1 65535
    int
    default 1024
    help
        The kernel maintains a mapping of 16-bit VPIDs to VCPUs. This option
        should be sized as small as possible to save memory, but be at least
        the number of VCPUs that will be run for optimum performance

config PAE_PAGING
    bool "Use PAE Paging"
    depends on ARCH_IA32
    default n
    help
        PAE paging uses 4K/2M pages and has three levels of paging. If this
        is not used the old 32-bit paging with 4K/4M pages will be used

config HUGE_PAGE
    bool "Use 1GB Huge Page"
    depends on ARCH_X86_64
    default y
    help
        Add support for 1GB huge page. Not all recent processor models support
        this feature.

config SUPPORT_PCID
    bool "Support Process Context IDentifiers"
    depends on ARCH_X86_64
    default y
    help
        Add support for PCIDs (aka hardware ASIDs). Not all processor models
        support this feature

choice
    prompt "Kernel syscall style"
    depends on ARCH_X86
    default SYSENTER if ARCH_IA32
    default SYSCALL if ARCH_X86_64
    help
        The kernel only ever supports one method of performing syscalls
        at a time. This config should be set to the most efficient one
        that is support by the hardware the system will run on

    config SYSENTER
        bool "sysenter+sysexit"
    config SYSCALL
        depends on ARCH_X86_64
        bool "syscall+sysret"
endchoice

choice
    prompt "FPU state implementation"
    depends on ARCH_X86
    default FXSAVE
    help
        Choose the method that FPU state is stored in. This directly
        affects the method used to save and rrestore it
    config FXSAVE
        bool "FXSAVE"
        help
            This chooses the legacy 512-byte region used by the
            fxsave and fxrstor functions
    config XSAVE
        bool "XSAVE"
        help
            This chooses the variable xsave region, and enables the
            ability to use any of the xsave variants to save and
            restore. The actual size of the region is dependent on
            the features enabled.
endchoice

choice
    prompt "XSAVE variant"
    depends on XSAVE
    default XSAVE_XSAVEOPT
    help
        The XSAVE area supports multiple instructions to save
        and restore to it. These instructions are dependent upon
        specific CPU support. See Chapter 13 of Volume 1 of the
        Intel Architectures SOftware Developers Manual for
        discussion on the init and modified optimizations

    config XSAVE_XSAVE
        bool "XSAVE"
        help
            Original XSAVE instruction. This is the only XSAVE
            instruction that is guaranteed to exist if XSAVE
            is present
    config XSAVE_XSAVEC
        bool "XSAVEC"
        help
            Save state with compaction. This compaction has
            to do with minimizing the total size of XSAVE buffer,
            if using non contiguous features, XSAVEC will attempt
            to use the init optimization when saving
    config XSAVE_XSAVEOPT
        bool "XSAVEOPT"
        help
            Save state taking advantage of both the init
            optimization and modified optimization
    config XSAVE_XSAVES
        bool "XSAVES"
        help
            Save state taking advantage of the modified
            optimization. This instruction is only
            available in OS code, and is the preferred
            save method if it exists
endchoice

config XSAVE_FEATURE_SET
    int "XSAVE feature set"
    depends on XSAVE
    default 3
    help
        XSAVE can save and restore the state for various
        features through the use of the feature mask. This
        config option represents the feature mask that we
        want to support. The CPU must support all bits
        in this feature mask. Current known bits are
        0 - FPU
        1 - SSE
        2 - AVX
        FPU and SSE is guaranteed to exist if XSAVE exists

config XSAVE_SIZE
    int "XSAVE region size"
    depends on ARCH_X86
    default 576 if XSAVE
    default 512 if !XSAVE
    help
        The size of the XSAVE region. This is dependent
        upon the features in XSAVE_FEATURE_SET that have
        been requested. Default is 576 for the FPU and
        SSE state, unless XSAVE is not in use then it
        should be 512 for the legacy FXSAVE region

config X86_FPU_MAX_RESTORES_SINCE_SWITCH
    int "Max thread restores without switching FPU"
    default 64
    help
        This option is a heuristic to attempt to detect when the FPU is no
        longer in use, allowing the kernel to save the FPU state out so that
        the FPU does not have to be enabled/disabled every thread swith. Every
        time we restore a thread and there is active FPU state, we increment
        this setting and if it exceeds this threshold we switch to the NULL
        state.

choice
    prompt "Setting FS/GS Base Addresses"
    depends on ARCH_X86
    default FSGSBASE_INST if ARCH_X86_64
    default FSGSBASE_GDT  if ARCH_IA32
    help
        There are three ways to to set FS/GS base addresses:
        IA32_FS/GS_GDT, IA32_FS/GS_BASE_MSR, and fsgsbase instructions.
        IA32_FS/GS_GDT and IA32_FS/GS_BASE_MSR are availble for 32-bit.
        IA32_FS/GS_BASE_MSR and fsgsbase instructions are available for 64-bit.

    config FSGSBASE_GDT
        bool "IA32_FS/GS_GDT"
        depends on ARCH_IA32
        help
            Use GDT entries.

    config FSGSBASE_MSR
        bool "IA32_FS/GS_BASE MSRs"
        depends on ARCH_X86
        help
            Use MSRs to change base addresses.

    config FSGSBASE_INST
        bool "FSGSBASE Instructions"
        depends on ARCH_X86_64
        help
            Use rdfs/gsbase, wrfs/gsbase instructions to change base adddresses.
endchoice
