/* automatically generated by rust-bindgen 0.72.1 */

#[repr(C)]
pub struct __BindgenUnionField<T>(::core::marker::PhantomData<T>);
impl<T> __BindgenUnionField<T> {
    #[inline]
    pub const fn new() -> Self {
        __BindgenUnionField(::core::marker::PhantomData)
    }
    #[inline]
    pub unsafe fn as_ref(&self) -> &T {
        ::core::mem::transmute(self)
    }
    #[inline]
    pub unsafe fn as_mut(&mut self) -> &mut T {
        ::core::mem::transmute(self)
    }
}
impl<T> ::core::default::Default for __BindgenUnionField<T> {
    #[inline]
    fn default() -> Self {
        Self::new()
    }
}
impl<T> ::core::clone::Clone for __BindgenUnionField<T> {
    #[inline]
    fn clone(&self) -> Self {
        *self
    }
}
impl<T> ::core::marker::Copy for __BindgenUnionField<T> {}
impl<T> ::core::fmt::Debug for __BindgenUnionField<T> {
    fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
        fmt.write_str("__BindgenUnionField")
    }
}
impl<T> ::core::hash::Hash for __BindgenUnionField<T> {
    fn hash<H: ::core::hash::Hasher>(&self, _state: &mut H) {}
}
impl<T> ::core::cmp::PartialEq for __BindgenUnionField<T> {
    fn eq(&self, _other: &__BindgenUnionField<T>) -> bool {
        true
    }
}
impl<T> ::core::cmp::Eq for __BindgenUnionField<T> {}
/// Default page-locked allocation flag.
pub const cudaHostAllocDefault: u32 = 0;
/// Pinned memory accessible by all CUDA contexts.
pub const cudaHostAllocPortable: u32 = 1;
/// Map allocation into device space.
pub const cudaHostAllocMapped: u32 = 2;
/// Write-combined memory.
pub const cudaHostAllocWriteCombined: u32 = 4;
/// Default host memory registration flag.
pub const cudaHostRegisterDefault: u32 = 0;
/// Pinned memory accessible by all CUDA contexts.
pub const cudaHostRegisterPortable: u32 = 1;
/// Map registered memory into device space.
pub const cudaHostRegisterMapped: u32 = 2;
/// Memory-mapped I/O space.
pub const cudaHostRegisterIoMemory: u32 = 4;
/// Memory-mapped read-only.
pub const cudaHostRegisterReadOnly: u32 = 8;
/// Default peer addressing enable flag.
pub const cudaPeerAccessDefault: u32 = 0;
/// Default stream flag.
pub const cudaStreamDefault: u32 = 0;
/// Stream does not synchronize with stream 0 (the NULL stream).
pub const cudaStreamNonBlocking: u32 = 1;
/// Default event record flag.
pub const cudaEventRecordDefault: u32 = 0;
/// Event is captured in the graph as an external event node when performing stream capture.
pub const cudaEventRecordExternal: u32 = 1;
#[repr(C)]
#[derive(Debug, Default, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct dim3 {
    pub x: ::core::ffi::c_uint,
    pub y: ::core::ffi::c_uint,
    pub z: ::core::ffi::c_uint,
}
/// Channel format kind.
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaChannelFormatKind {
    /// Signed channel format.
    cudaChannelFormatKindSigned = 0,
    /// Unsigned channel format.
    cudaChannelFormatKindUnsigned = 1,
    /// Float channel format.
    cudaChannelFormatKindFloat = 2,
    /// No channel format.
    cudaChannelFormatKindNone = 3,
    /// Unsigned 8-bit integers, planar 4:2:0 YUV format.
    cudaChannelFormatKindNV12 = 4,
    /// 1 channel unsigned 8-bit normalized integer.
    cudaChannelFormatKindUnsignedNormalized8X1 = 5,
    /// 2 channel unsigned 8-bit normalized integer.
    cudaChannelFormatKindUnsignedNormalized8X2 = 6,
    /// 4 channel unsigned 8-bit normalized integer.
    cudaChannelFormatKindUnsignedNormalized8X4 = 7,
    /// 1 channel unsigned 16-bit normalized integer.
    cudaChannelFormatKindUnsignedNormalized16X1 = 8,
    /// 2 channel unsigned 16-bit normalized integer.
    cudaChannelFormatKindUnsignedNormalized16X2 = 9,
    /// 4 channel unsigned 16-bit normalized integer.
    cudaChannelFormatKindUnsignedNormalized16X4 = 10,
    /// 1 channel signed 8-bit normalized integer.
    cudaChannelFormatKindSignedNormalized8X1 = 11,
    /// 2 channel signed 8-bit normalized integer.
    cudaChannelFormatKindSignedNormalized8X2 = 12,
    /// 4 channel signed 8-bit normalized integer.
    cudaChannelFormatKindSignedNormalized8X4 = 13,
    /// 1 channel signed 16-bit normalized integer.
    cudaChannelFormatKindSignedNormalized16X1 = 14,
    /// 2 channel signed 16-bit normalized integer.
    cudaChannelFormatKindSignedNormalized16X2 = 15,
    /// 4 channel signed 16-bit normalized integer.
    cudaChannelFormatKindSignedNormalized16X4 = 16,
    /// 4 channel unsigned normalized block-compressed (BC1 compression) format.
    cudaChannelFormatKindUnsignedBlockCompressed1 = 17,
    /// 4 channel unsigned normalized block-compressed (BC1 compression) format with sRGB encoding.
    cudaChannelFormatKindUnsignedBlockCompressed1SRGB = 18,
    /// 4 channel unsigned normalized block-compressed (BC2 compression) format.
    cudaChannelFormatKindUnsignedBlockCompressed2 = 19,
    /// 4 channel unsigned normalized block-compressed (BC2 compression) format with sRGB encoding.
    cudaChannelFormatKindUnsignedBlockCompressed2SRGB = 20,
    /// 4 channel unsigned normalized block-compressed (BC3 compression) format.
    cudaChannelFormatKindUnsignedBlockCompressed3 = 21,
    /// 4 channel unsigned normalized block-compressed (BC3 compression) format with sRGB encoding.
    cudaChannelFormatKindUnsignedBlockCompressed3SRGB = 22,
    /// 1 channel unsigned normalized block-compressed (BC4 compression) format.
    cudaChannelFormatKindUnsignedBlockCompressed4 = 23,
    /// 1 channel signed normalized block-compressed (BC4 compression) format.
    cudaChannelFormatKindSignedBlockCompressed4 = 24,
    /// 2 channel unsigned normalized block-compressed (BC5 compression) format.
    cudaChannelFormatKindUnsignedBlockCompressed5 = 25,
    /// 2 channel signed normalized block-compressed (BC5 compression) format.
    cudaChannelFormatKindSignedBlockCompressed5 = 26,
    /// 3 channel unsigned half-float block-compressed (BC6H compression) format.
    cudaChannelFormatKindUnsignedBlockCompressed6H = 27,
    /// 3 channel signed half-float block-compressed (BC6H compression) format.
    cudaChannelFormatKindSignedBlockCompressed6H = 28,
    /// 4 channel unsigned normalized block-compressed (BC7 compression) format.
    cudaChannelFormatKindUnsignedBlockCompressed7 = 29,
    /// 4 channel unsigned normalized block-compressed (BC7 compression) format with sRGB encoding.
    cudaChannelFormatKindUnsignedBlockCompressed7SRGB = 30,
    /// 4 channel unsigned normalized (10-bit, 10-bit, 10-bit, 2-bit) format.
    cudaChannelFormatKindUnsignedNormalized1010102 = 31,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct CUdevResourceDesc_st {
    _unused: [u8; 0],
}
/// An opaque descriptor handle. The descriptor encapsulates multiple created and configured resources. Created via cudaDeviceResourceGenerateDesc.
pub type cudaDevResourceDesc_t = *mut CUdevResourceDesc_st;
/// An opaque handle to a CUDA execution context. It represents an execution context created via CUDA Runtime APIs such as [cudaGreenCtxCreate](#cudaGreenCtxCreate "Creates a green context with a specified set of resources.").
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct cudaExecutionContext_st {
    _unused: [u8; 0],
}
/// An opaque handle to a CUDA execution context. It represents an execution context created via CUDA Runtime APIs such as [cudaGreenCtxCreate](#cudaGreenCtxCreate "Creates a green context with a specified set of resources.").
pub type cudaExecutionContext_t = *mut cudaExecutionContext_st;
/// CUDA Channel format descriptor.
#[repr(C)]
#[derive(Debug, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaChannelFormatDesc {
    /// x.
    pub x: ::core::ffi::c_int,
    /// y.
    pub y: ::core::ffi::c_int,
    /// z.
    pub z: ::core::ffi::c_int,
    /// w.
    pub w: ::core::ffi::c_int,
    /// Channel format kind.
    pub f: cudaChannelFormatKind,
}
impl Default for cudaChannelFormatDesc {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// CUDA memory types.
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaMemoryType {
    /// Unregistered memory.
    cudaMemoryTypeUnregistered = 0,
    /// Host memory.
    cudaMemoryTypeHost = 1,
    /// Device memory.
    cudaMemoryTypeDevice = 2,
    /// Managed memory.
    cudaMemoryTypeManaged = 3,
}
/// CUDA memory copy types.
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaMemcpyKind {
    /// Host -> Host.
    cudaMemcpyHostToHost = 0,
    /// Host -> Device.
    cudaMemcpyHostToDevice = 1,
    /// Device -> Host.
    cudaMemcpyDeviceToHost = 2,
    /// Device -> Device.
    cudaMemcpyDeviceToDevice = 3,
    /// Direction of the transfer is inferred from the pointer values. Requires unified virtual addressing.
    cudaMemcpyDefault = 4,
}
/// CUDA Pitched memory pointer
///
/// **See also:**
///
/// [make_cudaPitchedPtr](#make_cudaPitchedPtr "Returns a cudaPitchedPtr based on input parameters.")
#[repr(C)]
pub struct cudaPitchedPtr {
    /// Pointer to allocated memory.
    pub ptr: *mut ::core::ffi::c_void,
    /// Pitch of allocated memory in bytes.
    pub pitch: size_t,
    /// Logical width of allocation in elements.
    pub xsize: size_t,
    /// Logical height of allocation in elements.
    pub ysize: size_t,
}
impl Default for cudaPitchedPtr {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// CUDA extent
///
/// **See also:**
///
/// [make_cudaExtent](#make_cudaExtent "Returns a cudaExtent based on input parameters.")
#[repr(C)]
pub struct cudaExtent {
    /// Width in elements when referring to array memory, in bytes when referring to linear memory.
    pub width: size_t,
    /// Height in elements.
    pub height: size_t,
    /// Depth in elements.
    pub depth: size_t,
}
impl Default for cudaExtent {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// CUDA 3D position
///
/// **See also:**
///
/// [make_cudaPos](#make_cudaPos "Returns a cudaPos based on input parameters.")
#[repr(C)]
pub struct cudaPos {
    /// x.
    pub x: size_t,
    /// y.
    pub y: size_t,
    /// z.
    pub z: size_t,
}
impl Default for cudaPos {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// CUDA 3D memory copying parameters.
#[repr(C)]
pub struct cudaMemcpy3DParms {
    /// Source memory address.
    pub srcArray: cudaArray_t,
    /// Source position offset.
    pub srcPos: cudaPos,
    /// Pitched source memory address.
    pub srcPtr: cudaPitchedPtr,
    /// Destination memory address.
    pub dstArray: cudaArray_t,
    /// Destination position offset.
    pub dstPos: cudaPos,
    /// Pitched destination memory address.
    pub dstPtr: cudaPitchedPtr,
    /// Requested memory copy size.
    pub extent: cudaExtent,
    /// Type of transfer.
    pub kind: cudaMemcpyKind,
}
impl Default for cudaMemcpy3DParms {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// CUDA 3D cross-device memory copying parameters.
#[repr(C)]
pub struct cudaMemcpy3DPeerParms {
    /// Source memory address.
    pub srcArray: cudaArray_t,
    /// Source position offset.
    pub srcPos: cudaPos,
    /// Pitched source memory address.
    pub srcPtr: cudaPitchedPtr,
    /// Source device.
    pub srcDevice: ::core::ffi::c_int,
    /// Destination memory address.
    pub dstArray: cudaArray_t,
    /// Destination position offset.
    pub dstPos: cudaPos,
    /// Pitched destination memory address.
    pub dstPtr: cudaPitchedPtr,
    /// Destination device.
    pub dstDevice: ::core::ffi::c_int,
    /// Requested memory copy size.
    pub extent: cudaExtent,
}
impl Default for cudaMemcpy3DPeerParms {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// Specifies performance hint with [`cudaAccessPolicyWindow`] for hitProp and missProp members.
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaAccessProperty {
    /// Normal cache persistence.
    cudaAccessPropertyNormal = 0,
    /// Streaming access is less likely to persit from cache.
    cudaAccessPropertyStreaming = 1,
    /// Persisting access is more likely to persist in cache.
    cudaAccessPropertyPersisting = 2,
}
/// Specifies an access policy for a window, a contiguous extent of memory beginning at base_ptr and ending at base_ptr + num_bytes.
/// Partition into many segments and assign segments such that. sum of "hit segments" / window == approx. ratio. sum of "miss
/// segments" / window == approx 1-ratio. Segments and ratio specifications are fitted to the capabilities of the architecture.
/// Accesses in a hit segment apply the hitProp access policy. Accesses in a miss segment apply the missProp access policy.
#[repr(C)]
pub struct cudaAccessPolicyWindow {
    /// Starting address of the access policy window. CUDA driver may align it.
    pub base_ptr: *mut ::core::ffi::c_void,
    /// Size in bytes of the window policy. CUDA driver may restrict the maximum size and alignment.
    pub num_bytes: size_t,
    /// hitRatio specifies percentage of lines assigned hitProp, rest are assigned missProp.
    pub hitRatio: f32,
    /// [CUaccessProperty](../cuda-driver-api/group__CUDA__TYPES.html#group__CUDA__TYPES_1gbf4806140e86865b45fc144941a6ced5) set for hit.
    pub hitProp: cudaAccessProperty,
    /// [CUaccessProperty](../cuda-driver-api/group__CUDA__TYPES.html#group__CUDA__TYPES_1gbf4806140e86865b45fc144941a6ced5) set for miss. Must be either NORMAL or STREAMING.
    pub missProp: cudaAccessProperty,
}
impl Default for cudaAccessPolicyWindow {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaSynchronizationPolicy {
    cudaSyncPolicyAuto = 1,
    cudaSyncPolicySpin = 2,
    cudaSyncPolicyYield = 3,
    cudaSyncPolicyBlockingSync = 4,
}
/// Cluster scheduling policies. These may be passed to [cudaFuncSetAttribute](high-level-api.md#group__CUDART__HIGHLEVEL_1g61085e9f04656b92573af16072bbc78d "[C++ API] Set attributes for a given function").
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaClusterSchedulingPolicy {
    /// the default policy.
    cudaClusterSchedulingPolicyDefault = 0,
    /// spread the blocks within a cluster to the SMs.
    cudaClusterSchedulingPolicySpread = 1,
    /// allow the hardware to load-balance the blocks in a cluster to the SMs.
    cudaClusterSchedulingPolicyLoadBalancing = 2,
}
/// Flags for [cudaStreamUpdateCaptureDependencies](#cudaStreamUpdateCaptureDependencies "Update the set of dependencies in a capturing stream.")
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaStreamUpdateCaptureDependenciesFlags {
    /// Add new nodes to the dependency set.
    cudaStreamAddCaptureDependencies = 0,
    /// Replace the dependency set with the new nodes.
    cudaStreamSetCaptureDependencies = 1,
}
/// CUDA resource types.
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaResourceType {
    /// Array resource.
    cudaResourceTypeArray = 0,
    /// Mipmapped array resource.
    cudaResourceTypeMipmappedArray = 1,
    /// Linear resource.
    cudaResourceTypeLinear = 2,
    /// Pitch 2D resource.
    cudaResourceTypePitch2D = 3,
}
/// CUDA texture resource view formats.
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaResourceViewFormat {
    /// No resource view format (use underlying resource format).
    cudaResViewFormatNone = 0,
    /// 1 channel unsigned 8-bit integers.
    cudaResViewFormatUnsignedChar1 = 1,
    /// 2 channel unsigned 8-bit integers.
    cudaResViewFormatUnsignedChar2 = 2,
    /// 4 channel unsigned 8-bit integers.
    cudaResViewFormatUnsignedChar4 = 3,
    /// 1 channel signed 8-bit integers.
    cudaResViewFormatSignedChar1 = 4,
    /// 2 channel signed 8-bit integers.
    cudaResViewFormatSignedChar2 = 5,
    /// 4 channel signed 8-bit integers.
    cudaResViewFormatSignedChar4 = 6,
    /// 1 channel unsigned 16-bit integers.
    cudaResViewFormatUnsignedShort1 = 7,
    /// 2 channel unsigned 16-bit integers.
    cudaResViewFormatUnsignedShort2 = 8,
    /// 4 channel unsigned 16-bit integers.
    cudaResViewFormatUnsignedShort4 = 9,
    /// 1 channel signed 16-bit integers.
    cudaResViewFormatSignedShort1 = 10,
    /// 2 channel signed 16-bit integers.
    cudaResViewFormatSignedShort2 = 11,
    /// 4 channel signed 16-bit integers.
    cudaResViewFormatSignedShort4 = 12,
    /// 1 channel unsigned 32-bit integers.
    cudaResViewFormatUnsignedInt1 = 13,
    /// 2 channel unsigned 32-bit integers.
    cudaResViewFormatUnsignedInt2 = 14,
    /// 4 channel unsigned 32-bit integers.
    cudaResViewFormatUnsignedInt4 = 15,
    /// 1 channel signed 32-bit integers.
    cudaResViewFormatSignedInt1 = 16,
    /// 2 channel signed 32-bit integers.
    cudaResViewFormatSignedInt2 = 17,
    /// 4 channel signed 32-bit integers.
    cudaResViewFormatSignedInt4 = 18,
    /// 1 channel 16-bit floating point.
    cudaResViewFormatHalf1 = 19,
    /// 2 channel 16-bit floating point.
    cudaResViewFormatHalf2 = 20,
    /// 4 channel 16-bit floating point.
    cudaResViewFormatHalf4 = 21,
    /// 1 channel 32-bit floating point.
    cudaResViewFormatFloat1 = 22,
    /// 2 channel 32-bit floating point.
    cudaResViewFormatFloat2 = 23,
    /// 4 channel 32-bit floating point.
    cudaResViewFormatFloat4 = 24,
    /// Block compressed 1.
    cudaResViewFormatUnsignedBlockCompressed1 = 25,
    /// Block compressed 2.
    cudaResViewFormatUnsignedBlockCompressed2 = 26,
    /// Block compressed 3.
    cudaResViewFormatUnsignedBlockCompressed3 = 27,
    /// Block compressed 4 unsigned.
    cudaResViewFormatUnsignedBlockCompressed4 = 28,
    /// Block compressed 4 signed.
    cudaResViewFormatSignedBlockCompressed4 = 29,
    /// Block compressed 5 unsigned.
    cudaResViewFormatUnsignedBlockCompressed5 = 30,
    /// Block compressed 5 signed.
    cudaResViewFormatSignedBlockCompressed5 = 31,
    /// Block compressed 6 unsigned half-float.
    cudaResViewFormatUnsignedBlockCompressed6H = 32,
    /// Block compressed 6 signed half-float.
    cudaResViewFormatSignedBlockCompressed6H = 33,
    /// Block compressed 7.
    cudaResViewFormatUnsignedBlockCompressed7 = 34,
}
/// CUDA resource descriptor.
#[repr(C)]
pub struct cudaResourceDesc {
    /// Resource type.
    pub resType: cudaResourceType,
    pub res: cudaResourceDesc__bindgen_ty_1,
    /// Flags (must be zero).
    pub flags: ::core::ffi::c_uint,
}
#[repr(C)]
pub struct cudaResourceDesc__bindgen_ty_1 {
    pub array: __BindgenUnionField<cudaResourceDesc__bindgen_ty_1__bindgen_ty_1>,
    pub mipmap: __BindgenUnionField<cudaResourceDesc__bindgen_ty_1__bindgen_ty_2>,
    pub linear: __BindgenUnionField<cudaResourceDesc__bindgen_ty_1__bindgen_ty_3>,
    pub pitch2D: __BindgenUnionField<cudaResourceDesc__bindgen_ty_1__bindgen_ty_4>,
    pub reserved: __BindgenUnionField<cudaResourceDesc__bindgen_ty_1__bindgen_ty_5>,
    pub bindgen_union_field: [u64; 16usize],
}
#[repr(C)]
pub struct cudaResourceDesc__bindgen_ty_1__bindgen_ty_1 {
    pub array: cudaArray_t,
}
impl Default for cudaResourceDesc__bindgen_ty_1__bindgen_ty_1 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
#[repr(C)]
pub struct cudaResourceDesc__bindgen_ty_1__bindgen_ty_2 {
    pub mipmap: cudaMipmappedArray_t,
}
impl Default for cudaResourceDesc__bindgen_ty_1__bindgen_ty_2 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
#[repr(C)]
pub struct cudaResourceDesc__bindgen_ty_1__bindgen_ty_3 {
    pub devPtr: *mut ::core::ffi::c_void,
    pub desc: cudaChannelFormatDesc,
    pub sizeInBytes: size_t,
}
impl Default for cudaResourceDesc__bindgen_ty_1__bindgen_ty_3 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
#[repr(C)]
pub struct cudaResourceDesc__bindgen_ty_1__bindgen_ty_4 {
    pub devPtr: *mut ::core::ffi::c_void,
    pub desc: cudaChannelFormatDesc,
    pub width: size_t,
    pub height: size_t,
    pub pitchInBytes: size_t,
}
impl Default for cudaResourceDesc__bindgen_ty_1__bindgen_ty_4 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaResourceDesc__bindgen_ty_1__bindgen_ty_5 {
    pub reserved: [::core::ffi::c_int; 32usize],
}
impl Default for cudaResourceDesc__bindgen_ty_1 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
impl Default for cudaResourceDesc {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// CUDA resource view descriptor.
#[repr(C)]
pub struct cudaResourceViewDesc {
    /// Resource view format.
    pub format: cudaResourceViewFormat,
    /// Width of the resource view.
    pub width: size_t,
    /// Height of the resource view.
    pub height: size_t,
    /// Depth of the resource view.
    pub depth: size_t,
    /// First defined mipmap level.
    pub firstMipmapLevel: ::core::ffi::c_uint,
    /// Last defined mipmap level.
    pub lastMipmapLevel: ::core::ffi::c_uint,
    /// First layer index.
    pub firstLayer: ::core::ffi::c_uint,
    /// Last layer index.
    pub lastLayer: ::core::ffi::c_uint,
    /// Must be zero.
    pub reserved: [::core::ffi::c_uint; 16usize],
}
impl Default for cudaResourceViewDesc {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// CUDA pointer attributes.
#[repr(C)]
#[derive(Debug, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaPointerAttributes {
    pub type_: cudaMemoryType,
    /// The device against which the memory was allocated or registered. If the memory type is [cudaMemoryTypeDevice](group__CUDART__TYPES.html#group__CUDART__TYPES_1gg13de56a8fe75569530ecc3a3106e9b6d30c8466dd99563e4b1a43dd27bf7c743) then this identifies the device on which the memory referred physically resides. If the memory type is [cudaMemoryTypeHost](group__CUDART__TYPES.html#group__CUDART__TYPES_1gg13de56a8fe75569530ecc3a3106e9b6d9aa7478ab438d2dfb710c9100194a5be)[or::cudaMemoryTypeManaged](group__CUDART__TYPES.html#group__CUDART__TYPES_1gg13de56a8fe75569530ecc3a3106e9b6dbb20a4b61c559a4e7629fe60ac04b84e) then this identifies the device which was current when the memory was allocated or registered (and if that device is deinitialized
    /// then this allocation will vanish with that device's state).
    pub device: ::core::ffi::c_int,
    /// The address which may be dereferenced on the current device to access the memory or NULL if no such address exists.
    pub devicePointer: *mut ::core::ffi::c_void,
    /// The address which may be dereferenced on the host to access the memory or NULL if no such address exists.
    ///
    /// Note:
    ///
    /// CUDA doesn't check if unregistered memory is allocated so this field may contain invalid pointer if an invalid pointer has
    /// been passed to CUDA.
    pub hostPointer: *mut ::core::ffi::c_void,
    /// Must be zero.
    pub reserved: [::core::ffi::c_long; 8usize],
}
impl Default for cudaPointerAttributes {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// CUDA function attributes.
#[repr(C)]
pub struct cudaFuncAttributes {
    /// The size in bytes of statically-allocated shared memory per block required by this function. This does not include dynamically-allocated
    /// shared memory requested by the user at runtime.
    pub sharedSizeBytes: size_t,
    /// The size in bytes of user-allocated constant memory required by this function.
    pub constSizeBytes: size_t,
    /// The size in bytes of local memory used by each thread of this function.
    pub localSizeBytes: size_t,
    /// The maximum number of threads per block, beyond which a launch of the function would fail. This number depends on both the
    /// function and the device on which the function is currently loaded.
    pub maxThreadsPerBlock: ::core::ffi::c_int,
    /// The number of registers used by each thread of this function.
    pub numRegs: ::core::ffi::c_int,
    /// The PTX virtual architecture version for which the function was compiled. This value is the major PTX version \* 10 + the
    /// minor PTX version, so a PTX version 1.3 function would return the value 13.
    pub ptxVersion: ::core::ffi::c_int,
    /// The binary architecture version for which the function was compiled. This value is the major binary version \* 10 + the minor
    /// binary version, so a binary version 1.3 function would return the value 13.
    pub binaryVersion: ::core::ffi::c_int,
    /// The attribute to indicate whether the function has been compiled with user specified option "-Xptxas --dlcm=ca" set.
    pub cacheModeCA: ::core::ffi::c_int,
    /// The maximum size in bytes of dynamic shared memory per block for this function. Any launch must have a dynamic shared memory
    /// size smaller than this value.
    pub maxDynamicSharedSizeBytes: ::core::ffi::c_int,
    /// On devices where the L1 cache and shared memory use the same hardware resources, this sets the shared memory carveout preference,
    /// in percent of the maximum shared memory. Refer to [cudaDevAttrMaxSharedMemoryPerMultiprocessor](group__CUDART__TYPES.html#group__CUDART__TYPES_1gg49e2f8c2c0bd6fe264f2fc970912e5cdc478150b5ec1689a2944aaf7e25a5685). This is only a hint, and the driver can choose a different ratio if required to execute the function. See [cudaFuncSetAttribute](group__CUDART__HIGHLEVEL.html#group__CUDART__HIGHLEVEL_1g61085e9f04656b92573af16072bbc78d "[C++ API] Set attributes for a given function").
    pub preferredShmemCarveout: ::core::ffi::c_int,
    /// If this attribute is set, the kernel must launch with a valid cluster dimension specified.
    pub clusterDimMustBeSet: ::core::ffi::c_int,
    /// The required cluster width/height/depth in blocks. The values must either all be 0 or all be positive. The validity of the
    /// cluster dimensions is otherwise checked at launch time.
    ///
    /// If the value is set during compile time, it cannot be set at runtime. Setting it at runtime should return cudaErrorNotPermitted.
    /// See [cudaFuncSetAttribute](group__CUDART__HIGHLEVEL.html#group__CUDART__HIGHLEVEL_1g61085e9f04656b92573af16072bbc78d "[C++ API] Set attributes for a given function").
    pub requiredClusterWidth: ::core::ffi::c_int,
    pub requiredClusterHeight: ::core::ffi::c_int,
    pub requiredClusterDepth: ::core::ffi::c_int,
    /// The block scheduling policy of a function. See [cudaFuncSetAttribute](group__CUDART__HIGHLEVEL.html#group__CUDART__HIGHLEVEL_1g61085e9f04656b92573af16072bbc78d "[C++ API] Set attributes for a given function").
    pub clusterSchedulingPolicyPreference: ::core::ffi::c_int,
    /// Whether the function can be launched with non-portable cluster size. 1 is allowed, 0 is disallowed. A non-portable cluster
    /// size may only function on the specific SKUs the program is tested on. The launch might fail if the program is run on a different
    /// hardware platform.
    ///
    /// CUDA API provides [cudaOccupancyMaxActiveClusters](group__CUDART__HIGHLEVEL.html#group__CUDART__HIGHLEVEL_1gef663acab61362749507747e30fb210d "Given the kernel function (func) and launch configuration (config), return the maximum number of clusters that could co-exist on the target device in *numClusters.") to assist with checking whether the desired size can be launched on the current device.
    ///
    /// Portable Cluster Size
    ///
    /// A portable cluster size is guaranteed to be functional on all compute capabilities higher than the target compute capability.
    /// The portable cluster size for sm_90 is 8 blocks per cluster. This value may increase for future compute capabilities.
    ///
    /// The specific hardware unit may support higher cluster sizes that’s not guaranteed to be portable. See [cudaFuncSetAttribute](group__CUDART__HIGHLEVEL.html#group__CUDART__HIGHLEVEL_1g61085e9f04656b92573af16072bbc78d "[C++ API] Set attributes for a given function").
    pub nonPortableClusterSizeAllowed: ::core::ffi::c_int,
    pub reserved0: ::core::ffi::c_int,
    /// Reserved for future use.
    pub reserved: [::core::ffi::c_int; 15usize],
}
impl Default for cudaFuncAttributes {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// CUDA device compute modes.
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaComputeMode {
    /// Default compute mode (Multiple threads can use [cudaSetDevice()](#cudaSetDevice "Set device to be used for GPU executions.") with this device).
    cudaComputeModeDefault = 0,
    /// Compute-exclusive-thread mode (Only one thread in one process will be able to use [cudaSetDevice()](#cudaSetDevice "Set device to be used for GPU executions.") with this device).
    cudaComputeModeExclusive = 1,
    /// Compute-prohibited mode (No threads can use [cudaSetDevice()](#cudaSetDevice "Set device to be used for GPU executions.") with this device).
    cudaComputeModeProhibited = 2,
    /// Compute-exclusive-process mode (Many threads in one process will be able to use [cudaSetDevice()](#cudaSetDevice "Set device to be used for GPU executions.") with this device).
    cudaComputeModeExclusiveProcess = 3,
}
/// CUDA Limits.
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaLimit {
    /// GPU thread stack size.
    cudaLimitStackSize = 0,
    /// GPU printf FIFO size.
    cudaLimitPrintfFifoSize = 1,
    /// GPU malloc heap size.
    cudaLimitMallocHeapSize = 2,
    /// GPU device runtime synchronize depth.
    cudaLimitDevRuntimeSyncDepth = 3,
    /// GPU device runtime pending launch count.
    cudaLimitDevRuntimePendingLaunchCount = 4,
    /// A value between 0 and 128 that indicates the maximum fetch granularity of L2 (in Bytes). This is a hint.
    cudaLimitMaxL2FetchGranularity = 5,
    /// A size in bytes for L2 persisting lines cache size.
    cudaLimitPersistingL2CacheSize = 6,
}
/// Defines the allocation types available.
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaMemAllocationType {
    cudaMemAllocationTypeInvalid = 0,
    /// This allocation type is 'pinned', i.e. cannot migrate from its current location while the application is actively using it.
    cudaMemAllocationTypePinned = 1,
    /// This allocation type is managed memory.
    cudaMemAllocationTypeManaged = 2,
    cudaMemAllocationTypeMax = 2147483647,
}
/// CUDA-valid Atomic Operations.
#[repr(u32)]
#[derive(Debug, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub enum cudaAtomicOperation {
    cudaAtomicOperationIntegerAdd = 0,
    cudaAtomicOperationIntegerMin = 1,
    cudaAtomicOperationIntegerMax = 2,
    cudaAtomicOperationIntegerIncrement = 3,
    cudaAtomicOperationIntegerDecrement = 4,
    cudaAtomicOperationAnd = 5,
    cudaAtomicOperationOr = 6,
    cudaAtomicOperationXOR = 7,
    cudaAtomicOperationExchange = 8,
    cudaAtomicOperationCAS = 9,
    cudaAtomicOperationFloatAdd = 10,
    cudaAtomicOperationFloatMin = 11,
    cudaAtomicOperationFloatMax = 12,
}
/// CUDA UUID types.
#[repr(C)]
#[derive(Debug, Default, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct CUuuid_st {
    /// CUDA definition of UUID.
    pub bytes: [::core::ffi::c_char; 16usize],
}
/// CUDA device properties.
#[repr(C)]
pub struct cudaDeviceProp {
    /// ASCII string identifying device.
    pub name: [::core::ffi::c_char; 256usize],
    /// 16-byte unique identifier.
    pub uuid: cudaUUID_t,
    /// 8-byte locally unique identifier. Value is undefined on TCC and non-Windows platforms.
    pub luid: [::core::ffi::c_char; 8usize],
    /// LUID device node mask. Value is undefined on TCC and non-Windows platforms.
    pub luidDeviceNodeMask: ::core::ffi::c_uint,
    /// Global memory available on device in bytes.
    pub totalGlobalMem: size_t,
    /// Shared memory available per block in bytes.
    pub sharedMemPerBlock: size_t,
    /// 32-bit registers available per block.
    pub regsPerBlock: ::core::ffi::c_int,
    /// Warp size in threads.
    pub warpSize: ::core::ffi::c_int,
    /// Maximum pitch in bytes allowed by memory copies.
    pub memPitch: size_t,
    /// Maximum number of threads per block.
    pub maxThreadsPerBlock: ::core::ffi::c_int,
    /// Maximum size of each dimension of a block.
    pub maxThreadsDim: [::core::ffi::c_int; 3usize],
    /// Maximum size of each dimension of a grid.
    pub maxGridSize: [::core::ffi::c_int; 3usize],
    /// Constant memory available on device in bytes.
    pub totalConstMem: size_t,
    /// Major compute capability.
    pub major: ::core::ffi::c_int,
    /// Minor compute capability.
    pub minor: ::core::ffi::c_int,
    /// Alignment requirement for textures.
    pub textureAlignment: size_t,
    /// Pitch alignment requirement for texture references bound to pitched memory.
    pub texturePitchAlignment: size_t,
    /// Number of multiprocessors on device.
    pub multiProcessorCount: ::core::ffi::c_int,
    /// Device is integrated as opposed to discrete.
    pub integrated: ::core::ffi::c_int,
    /// Device can map host memory with cudaHostAlloc/cudaHostGetDevicePointer.
    pub canMapHostMemory: ::core::ffi::c_int,
    /// Maximum 1D texture size.
    pub maxTexture1D: ::core::ffi::c_int,
    /// Maximum 1D mipmapped texture size.
    pub maxTexture1DMipmap: ::core::ffi::c_int,
    /// Maximum 2D texture dimensions.
    pub maxTexture2D: [::core::ffi::c_int; 2usize],
    /// Maximum 2D mipmapped texture dimensions.
    pub maxTexture2DMipmap: [::core::ffi::c_int; 2usize],
    /// Maximum dimensions (width, height, pitch) for 2D textures bound to pitched memory.
    pub maxTexture2DLinear: [::core::ffi::c_int; 3usize],
    /// Maximum 2D texture dimensions if texture gather operations have to be performed.
    pub maxTexture2DGather: [::core::ffi::c_int; 2usize],
    /// Maximum 3D texture dimensions.
    pub maxTexture3D: [::core::ffi::c_int; 3usize],
    /// Maximum alternate 3D texture dimensions.
    pub maxTexture3DAlt: [::core::ffi::c_int; 3usize],
    /// Maximum Cubemap texture dimensions.
    pub maxTextureCubemap: ::core::ffi::c_int,
    /// Maximum 1D layered texture dimensions.
    pub maxTexture1DLayered: [::core::ffi::c_int; 2usize],
    /// Maximum 2D layered texture dimensions.
    pub maxTexture2DLayered: [::core::ffi::c_int; 3usize],
    /// Maximum Cubemap layered texture dimensions.
    pub maxTextureCubemapLayered: [::core::ffi::c_int; 2usize],
    /// Maximum 1D surface size.
    pub maxSurface1D: ::core::ffi::c_int,
    /// Maximum 2D surface dimensions.
    pub maxSurface2D: [::core::ffi::c_int; 2usize],
    /// Maximum 3D surface dimensions.
    pub maxSurface3D: [::core::ffi::c_int; 3usize],
    /// Maximum 1D layered surface dimensions.
    pub maxSurface1DLayered: [::core::ffi::c_int; 2usize],
    /// Maximum 2D layered surface dimensions.
    pub maxSurface2DLayered: [::core::ffi::c_int; 3usize],
    /// Maximum Cubemap surface dimensions.
    pub maxSurfaceCubemap: ::core::ffi::c_int,
    /// Maximum Cubemap layered surface dimensions.
    pub maxSurfaceCubemapLayered: [::core::ffi::c_int; 2usize],
    /// Alignment requirements for surfaces.
    pub surfaceAlignment: size_t,
    /// Device can possibly execute multiple kernels concurrently.
    pub concurrentKernels: ::core::ffi::c_int,
    /// Device has ECC support enabled.
    pub ECCEnabled: ::core::ffi::c_int,
    /// PCI bus ID of the device.
    pub pciBusID: ::core::ffi::c_int,
    /// PCI device ID of the device.
    pub pciDeviceID: ::core::ffi::c_int,
    /// PCI domain ID of the device.
    pub pciDomainID: ::core::ffi::c_int,
    /// 1 if device is a Tesla device using TCC driver, 0 otherwise.
    pub tccDriver: ::core::ffi::c_int,
    /// Number of asynchronous engines.
    pub asyncEngineCount: ::core::ffi::c_int,
    /// Device shares a unified address space with the host.
    pub unifiedAddressing: ::core::ffi::c_int,
    /// Global memory bus width in bits.
    pub memoryBusWidth: ::core::ffi::c_int,
    /// Size of L2 cache in bytes.
    pub l2CacheSize: ::core::ffi::c_int,
    /// Device's maximum l2 persisting lines capacity setting in bytes.
    pub persistingL2CacheMaxSize: ::core::ffi::c_int,
    /// Maximum resident threads per multiprocessor.
    pub maxThreadsPerMultiProcessor: ::core::ffi::c_int,
    /// Device supports stream priorities.
    pub streamPrioritiesSupported: ::core::ffi::c_int,
    /// Device supports caching globals in L1.
    pub globalL1CacheSupported: ::core::ffi::c_int,
    /// Device supports caching locals in L1.
    pub localL1CacheSupported: ::core::ffi::c_int,
    /// Shared memory available per multiprocessor in bytes.
    pub sharedMemPerMultiprocessor: size_t,
    /// 32-bit registers available per multiprocessor.
    pub regsPerMultiprocessor: ::core::ffi::c_int,
    /// Device supports allocating managed memory on this system.
    pub managedMemory: ::core::ffi::c_int,
    /// Device is on a multi-GPU board.
    pub isMultiGpuBoard: ::core::ffi::c_int,
    /// Unique identifier for a group of devices on the same multi-GPU board.
    pub multiGpuBoardGroupID: ::core::ffi::c_int,
    /// Link between the device and the host supports native atomic operations.
    pub hostNativeAtomicSupported: ::core::ffi::c_int,
    /// Device supports coherently accessing pageable memory without calling cudaHostRegister on it.
    pub pageableMemoryAccess: ::core::ffi::c_int,
    /// Device can coherently access managed memory concurrently with the CPU.
    pub concurrentManagedAccess: ::core::ffi::c_int,
    /// Device supports Compute Preemption.
    pub computePreemptionSupported: ::core::ffi::c_int,
    /// Device can access host registered memory at the same virtual address as the CPU.
    pub canUseHostPointerForRegisteredMem: ::core::ffi::c_int,
    /// Device supports launching cooperative kernels via [cudaLaunchCooperativeKernel](group__CUDART__HIGHLEVEL.html#group__CUDART__HIGHLEVEL_1g7c4cb6c44a6c4608da36c44374499b31 "Launches a device function.")
    pub cooperativeLaunch: ::core::ffi::c_int,
    /// Per device maximum shared memory per block usable by special opt in.
    pub sharedMemPerBlockOptin: size_t,
    /// Device accesses pageable memory via the host's page tables.
    pub pageableMemoryAccessUsesHostPageTables: ::core::ffi::c_int,
    /// Host can directly access managed memory on the device without migration.
    pub directManagedMemAccessFromHost: ::core::ffi::c_int,
    /// Maximum number of resident blocks per multiprocessor.
    pub maxBlocksPerMultiProcessor: ::core::ffi::c_int,
    /// The maximum value of [cudaAccessPolicyWindow::num_bytes](structcudaAccessPolicyWindow.html#structcudaAccessPolicyWindow_1bbd68021cb5c3cb1928bee0a2941eb24).
    pub accessPolicyMaxWindowSize: ::core::ffi::c_int,
    /// Shared memory reserved by CUDA driver per block in bytes.
    pub reservedSharedMemPerBlock: size_t,
    /// Device supports host memory registration via [cudaHostRegister](#cudaHostRegister "Registers an existing host memory range for use by CUDA.").
    pub hostRegisterSupported: ::core::ffi::c_int,
    /// 1 if the device supports sparse CUDA arrays and sparse CUDA mipmapped arrays, 0 otherwise.
    pub sparseCudaArraySupported: ::core::ffi::c_int,
    /// Device supports using the [cudaHostRegister](#cudaHostRegister "Registers an existing host memory range for use by CUDA.") flag cudaHostRegisterReadOnly to register memory that must be mapped as read-only to the GPU.
    pub hostRegisterReadOnlySupported: ::core::ffi::c_int,
    /// External timeline semaphore interop is supported on the device.
    pub timelineSemaphoreInteropSupported: ::core::ffi::c_int,
    /// 1 if the device supports using the cudaMallocAsync and cudaMemPool family of APIs, 0 otherwise.
    pub memoryPoolsSupported: ::core::ffi::c_int,
    /// 1 if the device supports GPUDirect RDMA APIs, 0 otherwise.
    pub gpuDirectRDMASupported: ::core::ffi::c_int,
    /// Bitmask to be interpreted according to the [cudaFlushGPUDirectRDMAWritesOptions](#cudaFlushGPUDirectRDMAWritesOptions) enum.
    pub gpuDirectRDMAFlushWritesOptions: ::core::ffi::c_uint,
    /// See the [cudaGPUDirectRDMAWritesOrdering](#cudaGPUDirectRDMAWritesOrdering) enum for numerical values.
    pub gpuDirectRDMAWritesOrdering: ::core::ffi::c_int,
    /// Bitmask of handle types supported with mempool-based IPC.
    pub memoryPoolSupportedHandleTypes: ::core::ffi::c_uint,
    /// 1 if the device supports deferred mapping CUDA arrays and CUDA mipmapped arrays.
    pub deferredMappingCudaArraySupported: ::core::ffi::c_int,
    /// Device supports IPC Events.
    pub ipcEventSupported: ::core::ffi::c_int,
    /// Indicates device supports cluster launch.
    pub clusterLaunch: ::core::ffi::c_int,
    /// Indicates device supports unified pointers.
    pub unifiedFunctionPointers: ::core::ffi::c_int,
    /// NUMA configuration of a device: value is of type [cudaDeviceNumaConfig](#cudaDeviceNumaConfig) enum.
    pub deviceNumaConfig: ::core::ffi::c_int,
    /// NUMA node ID of the GPU memory.
    pub deviceNumaId: ::core::ffi::c_int,
    /// Indicates if contexts created on this device will be shared via MPS.
    pub mpsEnabled: ::core::ffi::c_int,
    /// NUMA ID of the host node closest to the device or -1 when system does not support NUMA.
    pub hostNumaId: ::core::ffi::c_int,
    /// The combined 16-bit PCI device ID and 16-bit PCI vendor ID.
    pub gpuPciDeviceID: ::core::ffi::c_uint,
    /// The combined 16-bit PCI subsystem ID and 16-bit PCI subsystem vendor ID.
    pub gpuPciSubsystemID: ::core::ffi::c_uint,
    /// 1 if the device supports HostNuma location IPC between nodes in a multi-node system.
    pub hostNumaMultinodeIpcSupported: ::core::ffi::c_int,
    /// Reserved for future use.
    pub reserved: [::core::ffi::c_int; 56usize],
}
impl Default for cudaDeviceProp {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// External memory handle types.
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaExternalMemoryHandleType {
    /// Handle is an opaque file descriptor.
    cudaExternalMemoryHandleTypeOpaqueFd = 1,
    /// Handle is an opaque shared NT handle.
    cudaExternalMemoryHandleTypeOpaqueWin32 = 2,
    /// Handle is an opaque, globally shared handle.
    cudaExternalMemoryHandleTypeOpaqueWin32Kmt = 3,
    /// Handle is a D3D12 heap object.
    cudaExternalMemoryHandleTypeD3D12Heap = 4,
    /// Handle is a D3D12 committed resource.
    cudaExternalMemoryHandleTypeD3D12Resource = 5,
    /// Handle is a shared NT handle to a D3D11 resource.
    cudaExternalMemoryHandleTypeD3D11Resource = 6,
    /// Handle is a globally shared handle to a D3D11 resource.
    cudaExternalMemoryHandleTypeD3D11ResourceKmt = 7,
    /// Handle is an NvSciBuf object.
    cudaExternalMemoryHandleTypeNvSciBuf = 8,
}
/// External memory handle descriptor.
#[repr(C)]
#[derive(Copy, Clone)]
pub struct cudaExternalMemoryHandleDesc {
    pub type_: cudaExternalMemoryHandleType,
    /// Valid NT handle. Must be NULL if 'name' is non-NULL.
    pub handle: cudaExternalMemoryHandleDesc__bindgen_ty_1,
    /// Size of the memory allocation.
    pub size: ::core::ffi::c_ulonglong,
    /// Flags must either be zero or [cudaExternalMemoryDedicated](#cudaExternalMemoryDedicated).
    pub flags: ::core::ffi::c_uint,
    /// Must be zero.
    pub reserved: [::core::ffi::c_uint; 16usize],
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union cudaExternalMemoryHandleDesc__bindgen_ty_1 {
    pub fd: ::core::ffi::c_int,
    pub win32: cudaExternalMemoryHandleDesc__bindgen_ty_1__bindgen_ty_1,
    pub nvSciBufObject: *const ::core::ffi::c_void,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaExternalMemoryHandleDesc__bindgen_ty_1__bindgen_ty_1 {
    pub handle: *mut ::core::ffi::c_void,
    pub name: *const ::core::ffi::c_void,
}
impl Default for cudaExternalMemoryHandleDesc__bindgen_ty_1__bindgen_ty_1 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
impl Default for cudaExternalMemoryHandleDesc__bindgen_ty_1 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
impl Default for cudaExternalMemoryHandleDesc {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// External memory buffer descriptor.
#[repr(C)]
#[derive(Debug, Default, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaExternalMemoryBufferDesc {
    /// Offset into the memory object where the buffer's base is.
    pub offset: ::core::ffi::c_ulonglong,
    /// Size of the buffer.
    pub size: ::core::ffi::c_ulonglong,
    /// Flags reserved for future use. Must be zero.
    pub flags: ::core::ffi::c_uint,
    /// Must be zero.
    pub reserved: [::core::ffi::c_uint; 16usize],
}
/// External memory mipmap descriptor.
#[repr(C)]
pub struct cudaExternalMemoryMipmappedArrayDesc {
    /// Offset into the memory object where the base level of the mipmap chain is.
    pub offset: ::core::ffi::c_ulonglong,
    /// Format of base level of the mipmap chain.
    pub formatDesc: cudaChannelFormatDesc,
    /// Dimensions of base level of the mipmap chain.
    pub extent: cudaExtent,
    /// Flags associated with CUDA mipmapped arrays. See [cudaMallocMipmappedArray](#cudaMallocMipmappedArray "Allocate a mipmapped array on the device.")
    pub flags: ::core::ffi::c_uint,
    /// Total number of levels in the mipmap chain.
    pub numLevels: ::core::ffi::c_uint,
    /// Must be zero.
    pub reserved: [::core::ffi::c_uint; 16usize],
}
impl Default for cudaExternalMemoryMipmappedArrayDesc {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// External semaphore handle types.
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaExternalSemaphoreHandleType {
    /// Handle is an opaque file descriptor.
    cudaExternalSemaphoreHandleTypeOpaqueFd = 1,
    /// Handle is an opaque shared NT handle.
    cudaExternalSemaphoreHandleTypeOpaqueWin32 = 2,
    /// Handle is an opaque, globally shared handle.
    cudaExternalSemaphoreHandleTypeOpaqueWin32Kmt = 3,
    /// Handle is a shared NT handle referencing a D3D12 fence object.
    cudaExternalSemaphoreHandleTypeD3D12Fence = 4,
    /// Handle is a shared NT handle referencing a D3D11 fence object.
    cudaExternalSemaphoreHandleTypeD3D11Fence = 5,
    /// Opaque handle to NvSciSync Object.
    cudaExternalSemaphoreHandleTypeNvSciSync = 6,
    /// Handle is a shared NT handle referencing a D3D11 keyed mutex object.
    cudaExternalSemaphoreHandleTypeKeyedMutex = 7,
    /// Handle is a shared KMT handle referencing a D3D11 keyed mutex object.
    cudaExternalSemaphoreHandleTypeKeyedMutexKmt = 8,
    /// Handle is an opaque handle file descriptor referencing a timeline semaphore.
    cudaExternalSemaphoreHandleTypeTimelineSemaphoreFd = 9,
    /// Handle is an opaque handle file descriptor referencing a timeline semaphore.
    cudaExternalSemaphoreHandleTypeTimelineSemaphoreWin32 = 10,
}
/// External semaphore handle descriptor.
#[repr(C)]
#[derive(Copy, Clone)]
pub struct cudaExternalSemaphoreHandleDesc {
    pub type_: cudaExternalSemaphoreHandleType,
    /// Valid NT handle. Must be NULL if 'name' is non-NULL.
    pub handle: cudaExternalSemaphoreHandleDesc__bindgen_ty_1,
    /// Flags reserved for the future. Must be zero.
    pub flags: ::core::ffi::c_uint,
    /// Must be zero.
    pub reserved: [::core::ffi::c_uint; 16usize],
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union cudaExternalSemaphoreHandleDesc__bindgen_ty_1 {
    pub fd: ::core::ffi::c_int,
    pub win32: cudaExternalSemaphoreHandleDesc__bindgen_ty_1__bindgen_ty_1,
    pub nvSciSyncObj: *const ::core::ffi::c_void,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaExternalSemaphoreHandleDesc__bindgen_ty_1__bindgen_ty_1 {
    pub handle: *mut ::core::ffi::c_void,
    pub name: *const ::core::ffi::c_void,
}
impl Default for cudaExternalSemaphoreHandleDesc__bindgen_ty_1__bindgen_ty_1 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
impl Default for cudaExternalSemaphoreHandleDesc__bindgen_ty_1 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
impl Default for cudaExternalSemaphoreHandleDesc {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// External semaphore signal parameters, compatible with driver type.
#[repr(C)]
#[derive(Copy, Clone)]
pub struct cudaExternalSemaphoreSignalParams {
    pub params: cudaExternalSemaphoreSignalParams__bindgen_ty_1,
    /// Only when [`cudaExternalSemaphoreSignalParams`] is used to signal a [cudaExternalSemaphore_t](#cudaExternalSemaphore_t) of type [cudaExternalSemaphoreHandleTypeNvSciSync](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggb35390be1e170db8671b0abfb57ad3d91f340d33a5242e6aeb3a6a528046f062), the valid flag is [cudaExternalSemaphoreSignalSkipNvSciBufMemSync](#cudaExternalSemaphoreSignalSkipNvSciBufMemSync): which indicates that while signaling the [cudaExternalSemaphore_t](#cudaExternalSemaphore_t), no memory synchronization operations should be performed for any external memory object imported as [cudaExternalMemoryHandleTypeNvSciBuf](group__CUDART__TYPES.html#group__CUDART__TYPES_1gg62ab2fcc2eb066702c3694148383749e6f8cf38ae8bb776722f29fe5f076bdcf). For all other types of [cudaExternalSemaphore_t](#cudaExternalSemaphore_t), flags must be zero.
    pub flags: ::core::ffi::c_uint,
    pub reserved: [::core::ffi::c_uint; 16usize],
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct cudaExternalSemaphoreSignalParams__bindgen_ty_1 {
    pub fence: cudaExternalSemaphoreSignalParams__bindgen_ty_1__bindgen_ty_1,
    pub nvSciSync: cudaExternalSemaphoreSignalParams__bindgen_ty_1__bindgen_ty_2,
    pub keyedMutex: cudaExternalSemaphoreSignalParams__bindgen_ty_1__bindgen_ty_3,
    pub reserved: [::core::ffi::c_uint; 12usize],
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaExternalSemaphoreSignalParams__bindgen_ty_1__bindgen_ty_1 {
    pub value: ::core::ffi::c_ulonglong,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union cudaExternalSemaphoreSignalParams__bindgen_ty_1__bindgen_ty_2 {
    pub fence: *mut ::core::ffi::c_void,
    pub reserved: ::core::ffi::c_ulonglong,
}
impl Default for cudaExternalSemaphoreSignalParams__bindgen_ty_1__bindgen_ty_2 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaExternalSemaphoreSignalParams__bindgen_ty_1__bindgen_ty_3 {
    pub key: ::core::ffi::c_ulonglong,
}
impl Default for cudaExternalSemaphoreSignalParams__bindgen_ty_1 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
impl Default for cudaExternalSemaphoreSignalParams {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// External semaphore wait parameters, compatible with driver type.
#[repr(C)]
#[derive(Copy, Clone)]
pub struct cudaExternalSemaphoreWaitParams {
    pub params: cudaExternalSemaphoreWaitParams__bindgen_ty_1,
    /// Only when [`cudaExternalSemaphoreSignalParams`] is used to signal a [cudaExternalSemaphore_t](#cudaExternalSemaphore_t) of type [cudaExternalSemaphoreHandleTypeNvSciSync](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggb35390be1e170db8671b0abfb57ad3d91f340d33a5242e6aeb3a6a528046f062), the valid flag is [cudaExternalSemaphoreSignalSkipNvSciBufMemSync](#cudaExternalSemaphoreSignalSkipNvSciBufMemSync): which indicates that while waiting for the [cudaExternalSemaphore_t](#cudaExternalSemaphore_t), no memory synchronization operations should be performed for any external memory object imported as [cudaExternalMemoryHandleTypeNvSciBuf](group__CUDART__TYPES.html#group__CUDART__TYPES_1gg62ab2fcc2eb066702c3694148383749e6f8cf38ae8bb776722f29fe5f076bdcf). For all other types of [cudaExternalSemaphore_t](#cudaExternalSemaphore_t), flags must be zero.
    pub flags: ::core::ffi::c_uint,
    pub reserved: [::core::ffi::c_uint; 16usize],
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct cudaExternalSemaphoreWaitParams__bindgen_ty_1 {
    pub fence: cudaExternalSemaphoreWaitParams__bindgen_ty_1__bindgen_ty_1,
    pub nvSciSync: cudaExternalSemaphoreWaitParams__bindgen_ty_1__bindgen_ty_2,
    pub keyedMutex: cudaExternalSemaphoreWaitParams__bindgen_ty_1__bindgen_ty_3,
    pub reserved: [::core::ffi::c_uint; 10usize],
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaExternalSemaphoreWaitParams__bindgen_ty_1__bindgen_ty_1 {
    pub value: ::core::ffi::c_ulonglong,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union cudaExternalSemaphoreWaitParams__bindgen_ty_1__bindgen_ty_2 {
    pub fence: *mut ::core::ffi::c_void,
    pub reserved: ::core::ffi::c_ulonglong,
}
impl Default for cudaExternalSemaphoreWaitParams__bindgen_ty_1__bindgen_ty_2 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaExternalSemaphoreWaitParams__bindgen_ty_1__bindgen_ty_3 {
    pub key: ::core::ffi::c_ulonglong,
    pub timeoutMs: ::core::ffi::c_uint,
}
impl Default for cudaExternalSemaphoreWaitParams__bindgen_ty_1 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
impl Default for cudaExternalSemaphoreWaitParams {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// Type of resource.
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaDevResourceType {
    cudaDevResourceTypeInvalid = 0,
    /// Streaming multiprocessors related information.
    cudaDevResourceTypeSm = 1,
    /// Workqueue configuration related information.
    cudaDevResourceTypeWorkqueueConfig = 1000,
    /// Pre-existing workqueue related information.
    cudaDevResourceTypeWorkqueue = 10000,
}
/// Data for SM-related resources All parameters in this structure are OUTPUT only. Do not write to any of the fields in this
/// structure.
#[repr(C)]
#[derive(Debug, Default, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaDevSmResource {
    /// The amount of streaming multiprocessors available in this resource.
    pub smCount: ::core::ffi::c_uint,
    /// The minimum number of streaming multiprocessors required to partition this resource.
    pub minSmPartitionSize: ::core::ffi::c_uint,
    /// The number of streaming multiprocessors in this resource that are guaranteed to be co-scheduled on the same GPU processing
    /// cluster. smCount will be a multiple of this value, unless the backfill flag is set.
    pub smCoscheduledAlignment: ::core::ffi::c_uint,
    /// The flags set on this SM resource. For available flags see [cudaDevSmResourceGroup_flags](#cudaDevSmResourceGroup_flags).
    pub flags: ::core::ffi::c_uint,
}
/// Sharing scope for workqueues.
#[repr(u32)]
#[derive(Debug, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub enum cudaDevWorkqueueConfigScope {
    /// Use all shared workqueue resources on the device. Default driver behaviour.
    cudaDevWorkqueueConfigScopeDeviceCtx = 0,
    /// When possible, use non-overlapping workqueue resources with other balanced green contexts.
    cudaDevWorkqueueConfigScopeGreenCtxBalanced = 1,
}
/// Data for workqueue configuration related resources.
#[repr(C)]
#[derive(Debug, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaDevWorkqueueConfigResource {
    /// The device on which the workqueue resources are available.
    pub device: ::core::ffi::c_int,
    /// The expected maximum number of concurrent stream-ordered workloads.
    pub wqConcurrencyLimit: ::core::ffi::c_uint,
    /// The sharing scope for the workqueue resources.
    pub sharingScope: cudaDevWorkqueueConfigScope,
}
impl Default for cudaDevWorkqueueConfigResource {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// Handle to a pre-existing workqueue related resource.
#[repr(C)]
#[derive(Debug, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaDevWorkqueueResource {
    /// Reserved for future use.
    pub reserved: [::core::ffi::c_uchar; 40usize],
}
impl Default for cudaDevWorkqueueResource {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaDevSmResourceGroupParams_st {
    pub smCount: ::core::ffi::c_uint,
    pub coscheduledSmCount: ::core::ffi::c_uint,
    pub preferredCoscheduledSmCount: ::core::ffi::c_uint,
    pub flags: ::core::ffi::c_uint,
    pub reserved: [::core::ffi::c_uint; 12usize],
}
/// Input data for splitting SMs.
pub type cudaDevSmResourceGroupParams = cudaDevSmResourceGroupParams_st;
#[repr(C)]
#[derive(Copy, Clone)]
pub struct cudaDevResource_st {
    pub type_: cudaDevResourceType,
    pub _internal_padding: [::core::ffi::c_uchar; 92usize],
    pub __bindgen_anon_1: cudaDevResource_st__bindgen_ty_1,
    pub nextResource: *mut cudaDevResource_st,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union cudaDevResource_st__bindgen_ty_1 {
    pub sm: cudaDevSmResource,
    pub wqConfig: cudaDevWorkqueueConfigResource,
    pub wq: cudaDevWorkqueueResource,
    pub _oversize: [::core::ffi::c_uchar; 40usize],
}
impl Default for cudaDevResource_st__bindgen_ty_1 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
impl Default for cudaDevResource_st {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// A tagged union describing different resources identified by the type field. This structure should not be directly modified
/// outside of the API that created it.
///
/// ```text
/// struct {
/// enum cudaDevResourceType
/// type;
/// union {
/// struct cudaDevSmResource
/// sm;
/// struct cudaDevWorkqueueConfigResource
/// wqConfig;
/// struct cudaDevWorkqueueResource
/// wq;
/// };
/// };
/// ```
///
/// * If type is cudaDevResourceTypeInvalid, this resoure is not valid and cannot be further accessed.
/// * If type is cudaDevResourceTypeSm, the [`cudaDevSmResource`] structure sm is filled in. For example, sm.smCount will reflect the amount of streaming multiprocessors available in this resource.
/// * If type is cudaDevResourceTypeWorkqueueConfig, the [`cudaDevWorkqueueConfigResource`] structure wqConfig is filled in.
/// * If type is cudaDevResourceTypeWorkqueue, the [`cudaDevWorkqueueResource`] structure wq is filled in.
pub type cudaDevResource = cudaDevResource_st;
/// CUDA GPU kernel node parameters.
#[repr(C)]
#[derive(Debug, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaKernelNodeParams {
    /// Kernel to launch.
    pub func: *mut ::core::ffi::c_void,
    /// Grid dimensions.
    pub gridDim: dim3,
    /// Block dimensions.
    pub blockDim: dim3,
    /// Dynamic shared-memory size per thread block in bytes.
    pub sharedMemBytes: ::core::ffi::c_uint,
    /// Array of pointers to individual kernel arguments.
    pub kernelParams: *mut *mut ::core::ffi::c_void,
    /// Pointer to kernel arguments in the "extra" format.
    pub extra: *mut *mut ::core::ffi::c_void,
}
impl Default for cudaKernelNodeParams {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// Event record node parameters.
#[repr(C)]
pub struct cudaEventRecordNodeParams {
    /// The event to record when the node executes.
    pub event: cudaEvent_t,
}
impl Default for cudaEventRecordNodeParams {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct CUgraphDeviceUpdatableNode_st {
    _unused: [u8; 0],
}
/// CUDA device node handle for device-side node update.
pub type cudaGraphDeviceNode_t = *mut CUgraphDeviceUpdatableNode_st;
/// Memory Synchronization Domain
///
/// A kernel can be launched in a specified memory synchronization domain that affects all memory operations issued by that kernel.
/// A memory barrier issued in one domain will only order memory operations in that domain, thus eliminating latency increase
/// from memory barriers ordering unrelated traffic.
///
/// By default, kernels are launched in domain 0. Kernel launched with cudaLaunchMemSyncDomainRemote will have a different domain ID. User may also alter the domain ID with [`cudaLaunchMemSyncDomainMap`] for a specific stream / graph node / kernel launch. See cudaLaunchAttributeMemSyncDomain, [cudaStreamSetAttribute](#cudaStreamSetAttribute "Sets stream attribute."), [cudaLaunchKernelEx](high-level-api.md#group__CUDART__HIGHLEVEL_1g81f2b11c6726c7b2f3fc54fc718eaf1c "Launches a CUDA function with launch-time configuration."), [cudaGraphKernelNodeSetAttribute](#cudaGraphKernelNodeSetAttribute "Sets node attribute.").
///
/// Memory operations done in kernels launched in different domains are considered system-scope distanced. In other words, a GPU
/// scoped memory synchronization is not sufficient for memory order to be observed by kernels in another memory synchronization
/// domain even if they are on the same GPU.
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaLaunchMemSyncDomain {
    /// Launch kernels in the default domain.
    cudaLaunchMemSyncDomainDefault = 0,
    /// Launch kernels in the remote domain.
    cudaLaunchMemSyncDomainRemote = 1,
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaLaunchMemSyncDomainMap_st {
    pub default_: ::core::ffi::c_uchar,
    pub remote: ::core::ffi::c_uchar,
}
/// Memory Synchronization Domain map
///
/// See [`cudaLaunchMemSyncDomain`].
///
/// By default, kernels are launched in domain 0. Kernel launched with [cudaLaunchMemSyncDomainRemote](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggafb98f7ea7b0397ed6503780f3e672d5ac477b14c4ce022e029a4c2523eaeec2) will have a different domain ID. User may also alter the domain ID with [`cudaLaunchMemSyncDomainMap`] for a specific stream / graph node / kernel launch. See [cudaLaunchAttributeMemSyncDomainMap](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b056fef6b4fb87bd2e289180c2ca5805094d).
///
/// Domain ID range is available through [cudaDevAttrMemSyncDomainCount](group__CUDART__TYPES.html#group__CUDART__TYPES_1gg49e2f8c2c0bd6fe264f2fc970912e5cd82ae431cc82ee71d008b4e8e9cac06ab).
pub type cudaLaunchMemSyncDomainMap = cudaLaunchMemSyncDomainMap_st;
/// Enum for defining applicability of portable cluster size, used with [cudaLaunchKernelEx](high-level-api.md#group__CUDART__HIGHLEVEL_1g81f2b11c6726c7b2f3fc54fc718eaf1c "Launches a CUDA function with launch-time configuration.")
#[repr(u32)]
#[derive(Debug, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub enum cudaLaunchAttributePortableClusterMode {
    /// The default to use for allowing non-portable cluster size on launch - uses current function attribute for cudaFuncAttributeNonPortableClusterSizeAllowed.
    cudaLaunchPortableClusterModeDefault = 0,
    /// Specifies that the cluster size requested must be a portable size.
    cudaLaunchPortableClusterModeRequirePortable = 1,
    /// Specifies that the cluster size requested may be a non-portable size.
    cudaLaunchPortableClusterModeAllowNonPortable = 2,
}
/// Shared memory related attributes for use with [cuLaunchKernelEx](../cuda-driver-api/group__CUDA__EXEC.html#group__CUDA__EXEC_1gb9c891eb6bb8f4089758e64c9c976db9).
#[repr(u32)]
#[derive(Debug, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub enum cudaSharedMemoryMode {
    /// The default to use for allowing non-portable shared memory size on launch - uses current function attributes for cudaFuncAttributeMaxDynamicSharedMemorySize.
    cudaSharedMemoryModeDefault = 0,
    /// Specifies that the shared memory size requested must be a portable size within cudaDevAttrMaxSharedMemoryPerBlock.
    cudaSharedMemoryModeRequirePortable = 1,
    /// Specifies that the shared memory size requested may be a non-portable size up to cudaDevAttrMaxSharedMemoryPerBlockOptin.
    cudaSharedMemoryModeAllowNonPortable = 2,
}
/// Launch attributes enum; used as id field of [`cudaLaunchAttribute`].
#[repr(u32)]
#[derive(
    Debug,
    Copy,
    Clone,
    Hash,
    PartialOrd,
    Ord,
    PartialEq,
    Eq,
    TryFromPrimitive,
    IntoPrimitive,
)]
pub enum cudaLaunchAttributeID {
    /// Ignored entry, for convenient composition.
    cudaLaunchAttributeIgnore = 0,
    /// Valid for streams, graph nodes, launches. See [cudaLaunchAttributeValue::accessPolicyWindow](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_12651ad62e74da106b5e84b2e269e3d2f).
    cudaLaunchAttributeAccessPolicyWindow = 1,
    /// Valid for graph nodes, launches. See [cudaLaunchAttributeValue::cooperative](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_165547cda37105f05546238637fef02d4).
    cudaLaunchAttributeCooperative = 2,
    /// Valid for streams. See [cudaLaunchAttributeValue::syncPolicy](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_1f1c0a1fba8d619e14a27e1a5ffe8eb4e).
    cudaLaunchAttributeSynchronizationPolicy = 3,
    /// Valid for graph nodes, launches. See [cudaLaunchAttributeValue::clusterDim](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_1874ddc728430198e4d36b376a09a2390).
    cudaLaunchAttributeClusterDimension = 4,
    /// Valid for graph nodes, launches. See [cudaLaunchAttributeValue::clusterSchedulingPolicyPreference](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_122bc4df8c928315c4d1a519d5bb7c200).
    cudaLaunchAttributeClusterSchedulingPolicyPreference = 5,
    /// Valid for launches. Setting [cudaLaunchAttributeValue::programmaticStreamSerializationAllowed](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_1ef5afeecd2e7bc285f24c309694b315f) to non-0 signals that the kernel will use programmatic means to resolve its stream dependency, so that the CUDA runtime should
    /// opportunistically allow the grid's execution to overlap with the previous kernel in the stream, if that kernel requests the
    /// overlap. The dependent launches can choose to wait on the dependency using the programmatic sync ([cudaGridDependencySynchronize()](#cudaGridDependencySynchronize "Programmatic grid dependency synchronization.") or equivalent PTX instructions).
    cudaLaunchAttributeProgrammaticStreamSerialization = 6,
    /// Valid for launches. Set [cudaLaunchAttributeValue::programmaticEvent](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_1c4994840dcc67e4fc568a0b68b881830) to record the event. Event recorded through this launch attribute is guaranteed to only trigger after all block in the associated
    /// kernel trigger the event. A block can trigger the event programmatically in a future CUDA release. A trigger can also be inserted
    /// at the beginning of each block's execution if triggerAtBlockStart is set to non-0. The dependent launches can choose to wait
    /// on the dependency using the programmatic sync ([cudaGridDependencySynchronize()](#cudaGridDependencySynchronize "Programmatic grid dependency synchronization.") or equivalent PTX instructions). Note that dependents (including the CPU thread calling [cudaEventSynchronize()](#cudaEventSynchronize "Waits for an event to complete.")) are not guaranteed to observe the release precisely when it is released. For example, [cudaEventSynchronize()](#cudaEventSynchronize "Waits for an event to complete.") may only observe the event trigger long after the associated kernel has completed. This recording type is primarily meant
    /// for establishing programmatic dependency between device tasks. Note also this type of dependency allows, but does not guarantee,
    /// concurrent execution of tasks.
    /// The event supplied must not be an interprocess or interop event. The event must disable timing (i.e. must be created with
    /// the [cudaEventDisableTiming](#cudaEventDisableTiming) flag set).
    cudaLaunchAttributeProgrammaticEvent = 7,
    /// Valid for streams, graph nodes, launches. See [cudaLaunchAttributeValue::priority](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_1fbb47c87ab6783ea8bf2740de62e0698).
    cudaLaunchAttributePriority = 8,
    /// Valid for streams, graph nodes, launches. See [cudaLaunchAttributeValue::memSyncDomainMap](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_11eac2ba78a074529a8f8f22a50cfe6f8).
    cudaLaunchAttributeMemSyncDomainMap = 9,
    /// Valid for streams, graph nodes, launches. See [cudaLaunchAttributeValue::memSyncDomain](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_188c32c6eab183c58133c77a6634a2f48).
    cudaLaunchAttributeMemSyncDomain = 10,
    /// Valid for graph nodes and launches. Set [cudaLaunchAttributeValue::preferredClusterDim](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_17862864bbc2343700bae285345d188ca) to allow the kernel launch to specify a preferred substitute cluster dimension. Blocks may be grouped according to either
    /// the dimensions specified with this attribute (grouped into a "preferred substitute cluster"), or the one specified with cudaLaunchAttributeClusterDimension attribute (grouped into a "regular cluster"). The cluster dimensions of a "preferred substitute cluster" shall be an integer
    /// multiple greater than zero of the regular cluster dimensions. The device will attempt - on a best-effort basis - to group
    /// thread blocks into preferred clusters over grouping them into regular clusters. When it deems necessary (primarily when the
    /// device temporarily runs out of physical resources to launch the larger preferred clusters), the device may switch to launch
    /// the regular clusters instead to attempt to utilize as much of the physical device resources as possible.
    /// Each type of cluster will have its enumeration / coordinate setup as if the grid consists solely of its type of cluster. For
    /// example, if the preferred substitute cluster dimensions double the regular cluster dimensions, there might be simultaneously
    /// a regular cluster indexed at (1,0,0), and a preferred cluster indexed at (1,0,0). In this example, the preferred substitute
    /// cluster (1,0,0) replaces regular clusters (2,0,0) and (3,0,0) and groups their blocks.
    /// This attribute will only take effect when a regular cluster dimension has been specified. The preferred substitute cluster
    /// dimension must be an integer multiple greater than zero of the regular cluster dimension and must divide the grid. It must
    /// also be no more than `maxBlocksPerCluster`, if it is set in the kernel's `__launch_bounds__`. Otherwise it must be less than
    /// the maximum value the driver can support. Otherwise, setting this attribute to a value physically unable to fit on any particular
    /// device is permitted.
    cudaLaunchAttributePreferredClusterDimension = 11,
    /// Valid for launches. Set [cudaLaunchAttributeValue::launchCompletionEvent](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_1263ce1e0ff682dedbabc39ddf0fcbd93) to record the event.
    /// Nominally, the event is triggered once all blocks of the kernel have begun execution. Currently this is a best effort. If
    /// a kernel B has a launch completion dependency on a kernel A, B may wait until A is complete. Alternatively, blocks of B may
    /// begin before all blocks of A have begun, for example if B can claim execution resources unavailable to A (e.g. they run on
    /// different GPUs) or if B is a higher priority than A. Exercise caution if such an ordering inversion could lead to deadlock.
    /// A launch completion event is nominally similar to a programmatic event with triggerAtBlockStart set except that it is not visible to [cudaGridDependencySynchronize()](#cudaGridDependencySynchronize "Programmatic grid dependency synchronization.") and can be used with compute capability less than 9.0.
    /// The event supplied must not be an interprocess or interop event. The event must disable timing (i.e. must be created with
    /// the [cudaEventDisableTiming](#cudaEventDisableTiming) flag set).
    cudaLaunchAttributeLaunchCompletionEvent = 12,
    /// Valid for graph nodes, launches. This attribute is graphs-only, and passing it to a launch in a non-capturing stream will
    /// result in an error.
    /// :cudaLaunchAttributeValue::deviceUpdatableKernelNode::deviceUpdatable can only be set to 0 or 1. Setting the field to 1 indicates
    /// that the corresponding kernel node should be device-updatable. On success, a handle will be returned via cudaLaunchAttributeValue::deviceUpdatableKernelNode::devNode
    /// which can be passed to the various device-side update functions to update the node's kernel parameters from within another
    /// kernel. For more information on the types of device updates that can be made, as well as the relevant limitations thereof,
    /// see [cudaGraphKernelNodeUpdatesApply](#cudaGraphKernelNodeUpdatesApply "Batch applies multiple kernel node updates.").
    /// Nodes which are device-updatable have additional restrictions compared to regular kernel nodes. Firstly, device-updatable
    /// nodes cannot be removed from their graph via [cudaGraphDestroyNode](#cudaGraphDestroyNode "Remove a node from the graph."). Additionally, once opted-in to this functionality, a node cannot opt out, and any attempt to set the deviceUpdatable attribute
    /// to 0 will result in an error. Device-updatable kernel nodes also cannot have their attributes copied to/from another kernel
    /// node via [cudaGraphKernelNodeCopyAttributes](#cudaGraphKernelNodeCopyAttributes "Copies attributes from source node to destination node."). Graphs containing one or more device-updatable nodes also do not allow multiple instantiation, and neither the graph nor
    /// its instantiated version can be passed to [cudaGraphExecUpdate](#cudaGraphExecUpdate "Check whether an executable graph can be updated with a graph and perform the update if possible.").
    /// If a graph contains device-updatable nodes and updates those nodes from the device from within the graph, the graph must be
    /// uploaded with [cuGraphUpload](../cuda-driver-api/group__CUDA__GRAPH.html#group__CUDA__GRAPH_1ga7eb9849e6e4604864a482b38f25be48) before it is launched. For such a graph, if host-side executable graph updates are made to the device-updatable nodes, the
    /// graph must be uploaded before it is launched again.
    cudaLaunchAttributeDeviceUpdatableKernelNode = 13,
    /// Valid for launches. On devices where the L1 cache and shared memory use the same hardware resources, setting [cudaLaunchAttributeValue::sharedMemCarveout](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_15b20c278c86e5f0cfb34cd91c70c1bdd) to a percentage between 0-100 signals sets the shared memory carveout preference in percent of the total shared memory for
    /// that kernel launch. This attribute takes precedence over cudaFuncAttributePreferredSharedMemoryCarveout. This is only a hint, and the driver can choose a different configuration if required for the launch.
    cudaLaunchAttributePreferredSharedMemoryCarveout = 14,
    /// Valid for streams, graph nodes, launches. This attribute is a hint to the CUDA runtime that the launch should attempt to make
    /// the kernel maximize its NVLINK utilization.
    /// When possible to honor this hint, CUDA will assume each block in the grid launch will carry out an even amount of NVLINK traffic,
    /// and make a best-effort attempt to adjust the kernel launch based on that assumption.
    /// This attribute is a hint only. CUDA makes no functional or performance guarantee. Its applicability can be affected by many
    /// different factors, including driver version (i.e. CUDA doesn't guarantee the performance characteristics will be maintained
    /// between driver versions or a driver update could alter or regress previously observed perf characteristics.) It also doesn't
    /// guarantee a successful result, i.e. applying the attribute may not improve the performance of either the targeted kernel or
    /// the encapsulating application.
    /// Valid values for [cudaLaunchAttributeValue::nvlinkUtilCentricScheduling](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_110531ffcea7ecf81f2ec785f1eeeeb48) are 0 (disabled) and 1 (enabled).
    cudaLaunchAttributeNvlinkUtilCentricScheduling = 16,
    /// Valid for graph nodes, launches. This indicates whether the kernel launch is allowed to use a non-portable cluster size. Valid
    /// values for [cudaLaunchAttributeValue::portableClusterSizeMode](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_136a3fac80c29bafc05cda73b5071e7a6) are values for [`cudaLaunchAttributePortableClusterMode`] Any other value will return cudaErrorInvalidValue.
    cudaLaunchAttributePortableClusterSizeMode = 17,
    /// Valid for graph nodes, launches. This indicates that the kernel launch is allowed to use a non-portable shared memory mode.
    cudaLaunchAttributeSharedMemoryMode = 18,
}
/// Launch attributes union; used as value field of [`cudaLaunchAttribute`].
#[repr(C)]
pub struct cudaLaunchAttributeValue {
    pub pad: __BindgenUnionField<[::core::ffi::c_char; 64usize]>,
    /// Value of launch attribute [cudaLaunchAttributeAccessPolicyWindow](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b056d5b649d899f88b86b6c80d3d56d674b3).
    pub accessPolicyWindow: __BindgenUnionField<cudaAccessPolicyWindow>,
    /// Value of launch attribute [cudaLaunchAttributeCooperative](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b056f067f02ce2135e937c3dde1e9c62cfc6). Nonzero indicates a cooperative kernel (see [cudaLaunchCooperativeKernel](group__CUDART__HIGHLEVEL.html#group__CUDART__HIGHLEVEL_1g7c4cb6c44a6c4608da36c44374499b31 "Launches a device function.")).
    pub cooperative: __BindgenUnionField<::core::ffi::c_int>,
    /// Value of launch attribute [cudaLaunchAttributeSynchronizationPolicy](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b05697a48816036826f84b85dc52bc7bc42b). cudaSynchronizationPolicy for work queued up in this stream.
    pub syncPolicy: __BindgenUnionField<cudaSynchronizationPolicy>,
    /// Value of launch attribute [cudaLaunchAttributeClusterDimension](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b0563de2ec80489ee6a8010335db69abc3ff) that represents the desired cluster dimensions for the kernel. Opaque type with the following fields:
    ///
    /// * x - The X dimension of the cluster, in blocks. Must be a divisor of the grid X dimension.
    /// * y - The Y dimension of the cluster, in blocks. Must be a divisor of the grid Y dimension.
    /// * z - The Z dimension of the cluster, in blocks. Must be a divisor of the grid Z dimension.
    pub clusterDim: __BindgenUnionField<cudaLaunchAttributeValue__bindgen_ty_1>,
    /// Value of launch attribute [cudaLaunchAttributeClusterSchedulingPolicyPreference](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b056cd9c1223027c72d7a5cdaf15483e438f). Cluster scheduling policy preference for the kernel.
    pub clusterSchedulingPolicyPreference: __BindgenUnionField<
        cudaClusterSchedulingPolicy,
    >,
    /// Value of launch attribute [cudaLaunchAttributeProgrammaticStreamSerialization](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b056ae1805b9ab2fb5ac320737f39617b501).
    pub programmaticStreamSerializationAllowed: __BindgenUnionField<::core::ffi::c_int>,
    /// Value of launch attribute [cudaLaunchAttributeProgrammaticEvent](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b056690bb55d13016cd9dfd841d467388773) with the following fields:
    ///
    /// * cudaEvent_t event - Event to fire when all blocks trigger it.
    /// * int flags; - Event record flags, see [cudaEventRecordWithFlags](#cudaEventRecordWithFlags "Records an event."). Does not accept [`cudaEventRecordExternal`].
    /// * int triggerAtBlockStart - If this is set to non-0, each block launch will automatically trigger the event.
    pub programmaticEvent: __BindgenUnionField<cudaLaunchAttributeValue__bindgen_ty_2>,
    /// Value of launch attribute [cudaLaunchAttributePriority](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b05678f4b9132edfc2b8799b9cf16c1020c9). Execution priority of the kernel.
    pub priority: __BindgenUnionField<::core::ffi::c_int>,
    /// Value of launch attribute [cudaLaunchAttributeMemSyncDomainMap](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b056fef6b4fb87bd2e289180c2ca5805094d). See [`cudaLaunchMemSyncDomainMap`].
    pub memSyncDomainMap: __BindgenUnionField<cudaLaunchMemSyncDomainMap>,
    /// Value of launch attribute [cudaLaunchAttributeMemSyncDomain](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b0564cf7f560204bcd328e64214e3c82a416). See [`cudaLaunchMemSyncDomain`].
    pub memSyncDomain: __BindgenUnionField<cudaLaunchMemSyncDomain>,
    /// Value of launch attribute [cudaLaunchAttributePreferredClusterDimension](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b056606609f73e12c84ccee8da7ee195a735) that represents the desired preferred cluster dimensions for the kernel. Opaque type with the following fields:
    ///
    /// * x - The X dimension of the preferred cluster, in blocks. Must be a divisor of the grid X dimension, and must be a multiple
    /// of the x field of [cudaLaunchAttributeValue::clusterDim](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_1874ddc728430198e4d36b376a09a2390).
    /// * y - The Y dimension of the preferred cluster, in blocks. Must be a divisor of the grid Y dimension, and must be a multiple
    /// of the y field of [cudaLaunchAttributeValue::clusterDim](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_1874ddc728430198e4d36b376a09a2390).
    /// * z - The Z dimension of the preferred cluster, in blocks. Must be equal to the z field of [cudaLaunchAttributeValue::clusterDim](unioncudaLaunchAttributeValue.html#unioncudaLaunchAttributeValue_1874ddc728430198e4d36b376a09a2390).
    pub preferredClusterDim: __BindgenUnionField<cudaLaunchAttributeValue__bindgen_ty_3>,
    /// Value of launch attribute [cudaLaunchAttributeLaunchCompletionEvent](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b0566ae5120e9f16194a1aaf16f2f88bbfaa) with the following fields:
    ///
    /// * cudaEvent_t event - Event to fire when the last block launches.
    /// * int flags - Event record flags, see [cudaEventRecordWithFlags](#cudaEventRecordWithFlags "Records an event."). Does not accept [`cudaEventRecordExternal`].
    pub launchCompletionEvent: __BindgenUnionField<
        cudaLaunchAttributeValue__bindgen_ty_4,
    >,
    /// Value of launch attribute [cudaLaunchAttributeDeviceUpdatableKernelNode](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b0567e9bce67c8f264f4365c1591b0ec4f01) with the following fields:
    ///
    /// * int deviceUpdatable - Whether or not the resulting kernel node should be device-updatable.
    /// * cudaGraphDeviceNode_t devNode - Returns a handle to pass to the various device-side update functions.
    pub deviceUpdatableKernelNode: __BindgenUnionField<
        cudaLaunchAttributeValue__bindgen_ty_5,
    >,
    /// Value of launch attribute [cudaLaunchAttributePreferredSharedMemoryCarveout](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b056dfb41f119b4d1be4b6074f5b4755c44d).
    pub sharedMemCarveout: __BindgenUnionField<::core::ffi::c_uint>,
    /// Value of launch attribute [cudaLaunchAttributeNvlinkUtilCentricScheduling](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b056ad08129f89788c8e914d6304fb0e08af).
    pub nvlinkUtilCentricScheduling: __BindgenUnionField<::core::ffi::c_uint>,
    /// Value of launch attribute [cudaLaunchAttributePortableClusterSizeMode](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b056c6b1e9e7c665f3c26e33c4738e33b3d4).
    pub portableClusterSizeMode: __BindgenUnionField<
        cudaLaunchAttributePortableClusterMode,
    >,
    /// Value of launch attribute [cudaLaunchAttributeSharedMemoryMode](group__CUDART__TYPES.html#group__CUDART__TYPES_1ggfc5ed48085f05863b1aeebb14934b056445c144f777a4306508cb45cdb49a341). See [`cudaSharedMemoryMode`] for acceptable values.
    pub sharedMemoryMode: __BindgenUnionField<cudaSharedMemoryMode>,
    pub bindgen_union_field: [u64; 8usize],
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaLaunchAttributeValue__bindgen_ty_1 {
    pub x: ::core::ffi::c_uint,
    pub y: ::core::ffi::c_uint,
    pub z: ::core::ffi::c_uint,
}
#[repr(C)]
pub struct cudaLaunchAttributeValue__bindgen_ty_2 {
    pub event: cudaEvent_t,
    pub flags: ::core::ffi::c_int,
    pub triggerAtBlockStart: ::core::ffi::c_int,
}
impl Default for cudaLaunchAttributeValue__bindgen_ty_2 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
#[repr(C)]
#[derive(Debug, Default, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaLaunchAttributeValue__bindgen_ty_3 {
    pub x: ::core::ffi::c_uint,
    pub y: ::core::ffi::c_uint,
    pub z: ::core::ffi::c_uint,
}
#[repr(C)]
pub struct cudaLaunchAttributeValue__bindgen_ty_4 {
    pub event: cudaEvent_t,
    pub flags: ::core::ffi::c_int,
}
impl Default for cudaLaunchAttributeValue__bindgen_ty_4 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
#[repr(C)]
#[derive(Debug, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub struct cudaLaunchAttributeValue__bindgen_ty_5 {
    pub deviceUpdatable: ::core::ffi::c_int,
    pub devNode: cudaGraphDeviceNode_t,
}
impl Default for cudaLaunchAttributeValue__bindgen_ty_5 {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
impl Default for cudaLaunchAttributeValue {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
#[repr(C)]
pub struct cudaLaunchAttribute_st {
    pub id: cudaLaunchAttributeID,
    pub pad: [::core::ffi::c_char; 4usize],
    pub val: cudaLaunchAttributeValue,
}
impl Default for cudaLaunchAttribute_st {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// Launch attribute.
pub type cudaLaunchAttribute = cudaLaunchAttribute_st;
/// CUDA extensible launch configuration.
#[repr(C)]
pub struct cudaLaunchConfig_st {
    /// Grid dimensions.
    pub gridDim: dim3,
    /// Block dimensions.
    pub blockDim: dim3,
    /// Dynamic shared-memory size per thread block in bytes.
    pub dynamicSmemBytes: size_t,
    /// Stream identifier.
    pub stream: cudaStream_t,
    /// List of attributes; nullable if [cudaLaunchConfig_t::numAttrs](structcudaLaunchConfig__t.html#structcudaLaunchConfig__t_17a2f01ab7e1e959017ce1c769f568841) == 0.
    pub attrs: *mut cudaLaunchAttribute,
    /// Number of attributes populated in [cudaLaunchConfig_t::attrs](structcudaLaunchConfig__t.html#structcudaLaunchConfig__t_16c9c2735da285f0dd11f92c2c2baecf8).
    pub numAttrs: ::core::ffi::c_uint,
}
impl Default for cudaLaunchConfig_st {
    fn default() -> Self {
        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
        unsafe {
            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
            s.assume_init()
        }
    }
}
/// CUDA extensible launch configuration.
pub type cudaLaunchConfig_t = cudaLaunchConfig_st;
#[repr(u32)]
#[derive(Debug, Copy, Clone, Hash, PartialOrd, Ord, PartialEq, Eq)]
pub enum CUDAlogLevel_enum {
    cudaLogLevelError = 0,
    cudaLogLevelWarning = 1,
}
pub use self::CUDAlogLevel_enum as cudaLogLevel;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct CUlogsCallbackEntry_st {
    _unused: [u8; 0],
}
pub type cudaLogsCallbackHandle = *mut CUlogsCallbackEntry_st;
pub type cudaLogIterator = ::core::ffi::c_uint;
