///Register `ISR` reader
pub type R = crate::R<ISRrs>;
///Field `SEIF` reader - Security error interrupt flag status
pub type SEIF_R = crate::BitReader;
///Field `XONEIF` reader - Execute-only execute-never error interrupt flag status
pub type XONEIF_R = crate::BitReader;
///Field `KEIF` reader - Key error interrupt flag status
pub type KEIF_R = crate::BitReader;
impl R {
    ///Bit 0 - Security error interrupt flag status
    #[inline(always)]
    pub fn seif(&self) -> SEIF_R {
        SEIF_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - Execute-only execute-never error interrupt flag status
    #[inline(always)]
    pub fn xoneif(&self) -> XONEIF_R {
        XONEIF_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - Key error interrupt flag status
    #[inline(always)]
    pub fn keif(&self) -> KEIF_R {
        KEIF_R::new(((self.bits >> 2) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ISR")
            .field("seif", &self.seif())
            .field("xoneif", &self.xoneif())
            .field("keif", &self.keif())
            .finish()
    }
}
/**OTFDEC interrupt status register

You can [`read`](crate::Reg::read) this register and get [`isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct ISRrs;
impl crate::RegisterSpec for ISRrs {
    type Ux = u32;
}
///`read()` method returns [`isr::R`](R) reader structure
impl crate::Readable for ISRrs {}
///`reset()` method sets ISR to value 0
impl crate::Resettable for ISRrs {
    const RESET_VALUE: u32 = 0;
}
