///Register `MIS` reader
pub type R = crate::R<MISrs>;
///Field `OVR_MIS` reader - Data buffer overrun/underrun masked interrupt status
pub type OVR_MIS_R = crate::BitReader;
impl R {
    ///Bit 1 - Data buffer overrun/underrun masked interrupt status
    #[inline(always)]
    pub fn ovr_mis(&self) -> OVR_MIS_R {
        OVR_MIS_R::new(((self.bits >> 1) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("MIS").field("ovr_mis", &self.ovr_mis()).finish()
    }
}
/**PSSI masked interrupt status register

You can [`read`](crate::Reg::read) this register and get [`mis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct MISrs;
impl crate::RegisterSpec for MISrs {
    type Ux = u32;
}
///`read()` method returns [`mis::R`](R) reader structure
impl crate::Readable for MISrs {}
///`reset()` method sets MIS to value 0
impl crate::Resettable for MISrs {
    const RESET_VALUE: u32 = 0;
}
