///Register `DEVR1` reader
pub type R = crate::R<DEVR1rs>;
///Register `DEVR1` writer
pub type W = crate::W<DEVR1rs>;
///Field `DA` reader - Assigned I3C dynamic address to target x (when the I3C acts as controller)
pub type DA_R = crate::FieldReader;
///Field `DA` writer - Assigned I3C dynamic address to target x (when the I3C acts as controller)
pub type DA_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
///Field `IBIACK` reader - IBI request acknowledge (when the I3C acts as controller)
pub type IBIACK_R = crate::BitReader;
///Field `IBIACK` writer - IBI request acknowledge (when the I3C acts as controller)
pub type IBIACK_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CRACK` reader - Controller-role request acknowledge (when the I3C acts as controller)
pub type CRACK_R = crate::BitReader;
///Field `CRACK` writer - Controller-role request acknowledge (when the I3C acts as controller)
pub type CRACK_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IBIDEN` reader - IBI data enable (when the I3C acts as controller)
pub type IBIDEN_R = crate::BitReader;
///Field `IBIDEN` writer - IBI data enable (when the I3C acts as controller)
pub type IBIDEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `SUSP` reader - Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)
pub type SUSP_R = crate::BitReader;
///Field `SUSP` writer - Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)
pub type SUSP_W<'a, REG> = crate::BitWriter<'a, REG>;
/**Field `DIS` reader - DA\[6:0\]
write disabled (when the I3C acts as controller)*/
pub type DIS_R = crate::BitReader;
impl R {
    ///Bits 1:7 - Assigned I3C dynamic address to target x (when the I3C acts as controller)
    #[inline(always)]
    pub fn da(&self) -> DA_R {
        DA_R::new(((self.bits >> 1) & 0x7f) as u8)
    }
    ///Bit 16 - IBI request acknowledge (when the I3C acts as controller)
    #[inline(always)]
    pub fn ibiack(&self) -> IBIACK_R {
        IBIACK_R::new(((self.bits >> 16) & 1) != 0)
    }
    ///Bit 17 - Controller-role request acknowledge (when the I3C acts as controller)
    #[inline(always)]
    pub fn crack(&self) -> CRACK_R {
        CRACK_R::new(((self.bits >> 17) & 1) != 0)
    }
    ///Bit 18 - IBI data enable (when the I3C acts as controller)
    #[inline(always)]
    pub fn ibiden(&self) -> IBIDEN_R {
        IBIDEN_R::new(((self.bits >> 18) & 1) != 0)
    }
    ///Bit 19 - Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)
    #[inline(always)]
    pub fn susp(&self) -> SUSP_R {
        SUSP_R::new(((self.bits >> 19) & 1) != 0)
    }
    /**Bit 31 - DA\[6:0\]
write disabled (when the I3C acts as controller)*/
    #[inline(always)]
    pub fn dis(&self) -> DIS_R {
        DIS_R::new(((self.bits >> 31) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DEVR1")
            .field("da", &self.da())
            .field("ibiack", &self.ibiack())
            .field("crack", &self.crack())
            .field("ibiden", &self.ibiden())
            .field("susp", &self.susp())
            .field("dis", &self.dis())
            .finish()
    }
}
impl W {
    ///Bits 1:7 - Assigned I3C dynamic address to target x (when the I3C acts as controller)
    #[inline(always)]
    pub fn da(&mut self) -> DA_W<DEVR1rs> {
        DA_W::new(self, 1)
    }
    ///Bit 16 - IBI request acknowledge (when the I3C acts as controller)
    #[inline(always)]
    pub fn ibiack(&mut self) -> IBIACK_W<DEVR1rs> {
        IBIACK_W::new(self, 16)
    }
    ///Bit 17 - Controller-role request acknowledge (when the I3C acts as controller)
    #[inline(always)]
    pub fn crack(&mut self) -> CRACK_W<DEVR1rs> {
        CRACK_W::new(self, 17)
    }
    ///Bit 18 - IBI data enable (when the I3C acts as controller)
    #[inline(always)]
    pub fn ibiden(&mut self) -> IBIDEN_W<DEVR1rs> {
        IBIDEN_W::new(self, 18)
    }
    ///Bit 19 - Suspend/stop I3C transfer on received IBI (when the I3C acts as controller)
    #[inline(always)]
    pub fn susp(&mut self) -> SUSP_W<DEVR1rs> {
        SUSP_W::new(self, 19)
    }
}
/**I3C device 1 characteristics register

You can [`read`](crate::Reg::read) this register and get [`devr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`devr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct DEVR1rs;
impl crate::RegisterSpec for DEVR1rs {
    type Ux = u32;
}
///`read()` method returns [`devr1::R`](R) reader structure
impl crate::Readable for DEVR1rs {}
///`write(|w| ..)` method takes [`devr1::W`](W) writer structure
impl crate::Writable for DEVR1rs {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
///`reset()` method sets DEVR1 to value 0
impl crate::Resettable for DEVR1rs {
    const RESET_VALUE: u32 = 0;
}
