///Register `PLL2DIVR` reader
pub type R = crate::R<PLL2DIVRrs>;
///Register `PLL2DIVR` writer
pub type W = crate::W<PLL2DIVRrs>;
///Field `PLL2N` reader - Multiplication factor for PLL2VCO
pub type PLL2N_R = crate::FieldReader<u16>;
///Field `PLL2N` writer - Multiplication factor for PLL2VCO
pub type PLL2N_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
///Field `PLL2P` reader - PLL2 DIVP division factor
pub type PLL2P_R = crate::FieldReader;
///Field `PLL2P` writer - PLL2 DIVP division factor
pub type PLL2P_W<'a, REG> = crate::FieldWriter<'a, REG, 7, u8, crate::Safe>;
///Field `PLL2Q` reader - PLL2 DIVQ division factor
pub type PLL2Q_R = crate::FieldReader;
///Field `PLL2Q` writer - PLL2 DIVQ division factor
pub type PLL2Q_W<'a, REG> = crate::FieldWriter<'a, REG, 7, u8, crate::Safe>;
///Field `PLL2R` reader - PLL2 DIVR division factor
pub type PLL2R_R = crate::FieldReader;
///Field `PLL2R` writer - PLL2 DIVR division factor
pub type PLL2R_W<'a, REG> = crate::FieldWriter<'a, REG, 7, u8, crate::Safe>;
impl R {
    ///Bits 0:8 - Multiplication factor for PLL2VCO
    #[inline(always)]
    pub fn pll2n(&self) -> PLL2N_R {
        PLL2N_R::new((self.bits & 0x01ff) as u16)
    }
    ///Bits 9:15 - PLL2 DIVP division factor
    #[inline(always)]
    pub fn pll2p(&self) -> PLL2P_R {
        PLL2P_R::new(((self.bits >> 9) & 0x7f) as u8)
    }
    ///Bits 16:22 - PLL2 DIVQ division factor
    #[inline(always)]
    pub fn pll2q(&self) -> PLL2Q_R {
        PLL2Q_R::new(((self.bits >> 16) & 0x7f) as u8)
    }
    ///Bits 24:30 - PLL2 DIVR division factor
    #[inline(always)]
    pub fn pll2r(&self) -> PLL2R_R {
        PLL2R_R::new(((self.bits >> 24) & 0x7f) as u8)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PLL2DIVR")
            .field("pll2n", &self.pll2n())
            .field("pll2p", &self.pll2p())
            .field("pll2q", &self.pll2q())
            .field("pll2r", &self.pll2r())
            .finish()
    }
}
impl W {
    ///Bits 0:8 - Multiplication factor for PLL2VCO
    #[inline(always)]
    pub fn pll2n(&mut self) -> PLL2N_W<PLL2DIVRrs> {
        PLL2N_W::new(self, 0)
    }
    ///Bits 9:15 - PLL2 DIVP division factor
    #[inline(always)]
    pub fn pll2p(&mut self) -> PLL2P_W<PLL2DIVRrs> {
        PLL2P_W::new(self, 9)
    }
    ///Bits 16:22 - PLL2 DIVQ division factor
    #[inline(always)]
    pub fn pll2q(&mut self) -> PLL2Q_W<PLL2DIVRrs> {
        PLL2Q_W::new(self, 16)
    }
    ///Bits 24:30 - PLL2 DIVR division factor
    #[inline(always)]
    pub fn pll2r(&mut self) -> PLL2R_W<PLL2DIVRrs> {
        PLL2R_W::new(self, 24)
    }
}
/**RCC PLL1 dividers register

You can [`read`](crate::Reg::read) this register and get [`pll2divr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pll2divr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct PLL2DIVRrs;
impl crate::RegisterSpec for PLL2DIVRrs {
    type Ux = u32;
}
///`read()` method returns [`pll2divr::R`](R) reader structure
impl crate::Readable for PLL2DIVRrs {}
///`write(|w| ..)` method takes [`pll2divr::W`](W) writer structure
impl crate::Writable for PLL2DIVRrs {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
///`reset()` method sets PLL2DIVR to value 0x0101_0280
impl crate::Resettable for PLL2DIVRrs {
    const RESET_VALUE: u32 = 0x0101_0280;
}
