///Register `CFGR2` reader
pub type R = crate::R<CFGR2rs>;
///Register `CFGR2` writer
pub type W = crate::W<CFGR2rs>;
/**BMC decoder Rx pre-filter enable The sampling clock is that of the receiver (that is, after pre-scaler).

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RXFILTDIS {
    ///0: Rx pre-filter enabled
    Enabled = 0,
    ///1: Rx pre-filter disabled
    Disabled = 1,
}
impl From<RXFILTDIS> for bool {
    #[inline(always)]
    fn from(variant: RXFILTDIS) -> Self {
        variant as u8 != 0
    }
}
///Field `RXFILTDIS` reader - BMC decoder Rx pre-filter enable The sampling clock is that of the receiver (that is, after pre-scaler).
pub type RXFILTDIS_R = crate::BitReader<RXFILTDIS>;
impl RXFILTDIS_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> RXFILTDIS {
        match self.bits {
            false => RXFILTDIS::Enabled,
            true => RXFILTDIS::Disabled,
        }
    }
    ///Rx pre-filter enabled
    #[inline(always)]
    pub fn is_enabled(&self) -> bool {
        *self == RXFILTDIS::Enabled
    }
    ///Rx pre-filter disabled
    #[inline(always)]
    pub fn is_disabled(&self) -> bool {
        *self == RXFILTDIS::Disabled
    }
}
///Field `RXFILTDIS` writer - BMC decoder Rx pre-filter enable The sampling clock is that of the receiver (that is, after pre-scaler).
pub type RXFILTDIS_W<'a, REG> = crate::BitWriter<'a, REG, RXFILTDIS>;
impl<'a, REG> RXFILTDIS_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///Rx pre-filter enabled
    #[inline(always)]
    pub fn enabled(self) -> &'a mut crate::W<REG> {
        self.variant(RXFILTDIS::Enabled)
    }
    ///Rx pre-filter disabled
    #[inline(always)]
    pub fn disabled(self) -> &'a mut crate::W<REG> {
        self.variant(RXFILTDIS::Disabled)
    }
}
/**BMC decoder Rx pre-filter sampling method Number of consistent consecutive samples before confirming a new value.

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RXFILT2N3 {
    ///0: 3 samples
    Samp3 = 0,
    ///1: 2 samples
    Samp2 = 1,
}
impl From<RXFILT2N3> for bool {
    #[inline(always)]
    fn from(variant: RXFILT2N3) -> Self {
        variant as u8 != 0
    }
}
///Field `RXFILT2N3` reader - BMC decoder Rx pre-filter sampling method Number of consistent consecutive samples before confirming a new value.
pub type RXFILT2N3_R = crate::BitReader<RXFILT2N3>;
impl RXFILT2N3_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> RXFILT2N3 {
        match self.bits {
            false => RXFILT2N3::Samp3,
            true => RXFILT2N3::Samp2,
        }
    }
    ///3 samples
    #[inline(always)]
    pub fn is_samp3(&self) -> bool {
        *self == RXFILT2N3::Samp3
    }
    ///2 samples
    #[inline(always)]
    pub fn is_samp2(&self) -> bool {
        *self == RXFILT2N3::Samp2
    }
}
///Field `RXFILT2N3` writer - BMC decoder Rx pre-filter sampling method Number of consistent consecutive samples before confirming a new value.
pub type RXFILT2N3_W<'a, REG> = crate::BitWriter<'a, REG, RXFILT2N3>;
impl<'a, REG> RXFILT2N3_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///3 samples
    #[inline(always)]
    pub fn samp3(self) -> &'a mut crate::W<REG> {
        self.variant(RXFILT2N3::Samp3)
    }
    ///2 samples
    #[inline(always)]
    pub fn samp2(self) -> &'a mut crate::W<REG> {
        self.variant(RXFILT2N3::Samp2)
    }
}
/**Force ClkReq clock request

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum FORCECLK {
    ///0: Do not force clock request
    NoForce = 0,
    ///1: Force clock request
    Force = 1,
}
impl From<FORCECLK> for bool {
    #[inline(always)]
    fn from(variant: FORCECLK) -> Self {
        variant as u8 != 0
    }
}
///Field `FORCECLK` reader - Force ClkReq clock request
pub type FORCECLK_R = crate::BitReader<FORCECLK>;
impl FORCECLK_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> FORCECLK {
        match self.bits {
            false => FORCECLK::NoForce,
            true => FORCECLK::Force,
        }
    }
    ///Do not force clock request
    #[inline(always)]
    pub fn is_no_force(&self) -> bool {
        *self == FORCECLK::NoForce
    }
    ///Force clock request
    #[inline(always)]
    pub fn is_force(&self) -> bool {
        *self == FORCECLK::Force
    }
}
///Field `FORCECLK` writer - Force ClkReq clock request
pub type FORCECLK_W<'a, REG> = crate::BitWriter<'a, REG, FORCECLK>;
impl<'a, REG> FORCECLK_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///Do not force clock request
    #[inline(always)]
    pub fn no_force(self) -> &'a mut crate::W<REG> {
        self.variant(FORCECLK::NoForce)
    }
    ///Force clock request
    #[inline(always)]
    pub fn force(self) -> &'a mut crate::W<REG> {
        self.variant(FORCECLK::Force)
    }
}
/**Wakeup from Stop mode enable Setting the bit enables the UCPD_ASYNC_INT signal.

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum WUPEN {
    ///0: Disabled
    Disabled = 0,
    ///1: Enabled
    Enabled = 1,
}
impl From<WUPEN> for bool {
    #[inline(always)]
    fn from(variant: WUPEN) -> Self {
        variant as u8 != 0
    }
}
///Field `WUPEN` reader - Wakeup from Stop mode enable Setting the bit enables the UCPD_ASYNC_INT signal.
pub type WUPEN_R = crate::BitReader<WUPEN>;
impl WUPEN_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> WUPEN {
        match self.bits {
            false => WUPEN::Disabled,
            true => WUPEN::Enabled,
        }
    }
    ///Disabled
    #[inline(always)]
    pub fn is_disabled(&self) -> bool {
        *self == WUPEN::Disabled
    }
    ///Enabled
    #[inline(always)]
    pub fn is_enabled(&self) -> bool {
        *self == WUPEN::Enabled
    }
}
///Field `WUPEN` writer - Wakeup from Stop mode enable Setting the bit enables the UCPD_ASYNC_INT signal.
pub type WUPEN_W<'a, REG> = crate::BitWriter<'a, REG, WUPEN>;
impl<'a, REG> WUPEN_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///Disabled
    #[inline(always)]
    pub fn disabled(self) -> &'a mut crate::W<REG> {
        self.variant(WUPEN::Disabled)
    }
    ///Enabled
    #[inline(always)]
    pub fn enabled(self) -> &'a mut crate::W<REG> {
        self.variant(WUPEN::Enabled)
    }
}
///Field `RXAFILTEN` reader - Rx analog filter enable Setting the bit enables the Rx analog filter required for optimum Power Delivery reception.
pub use WUPEN_R as RXAFILTEN_R;
///Field `RXAFILTEN` writer - Rx analog filter enable Setting the bit enables the Rx analog filter required for optimum Power Delivery reception.
pub use WUPEN_W as RXAFILTEN_W;
impl R {
    ///Bit 0 - BMC decoder Rx pre-filter enable The sampling clock is that of the receiver (that is, after pre-scaler).
    #[inline(always)]
    pub fn rxfiltdis(&self) -> RXFILTDIS_R {
        RXFILTDIS_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - BMC decoder Rx pre-filter sampling method Number of consistent consecutive samples before confirming a new value.
    #[inline(always)]
    pub fn rxfilt2n3(&self) -> RXFILT2N3_R {
        RXFILT2N3_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - Force ClkReq clock request
    #[inline(always)]
    pub fn forceclk(&self) -> FORCECLK_R {
        FORCECLK_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 3 - Wakeup from Stop mode enable Setting the bit enables the UCPD_ASYNC_INT signal.
    #[inline(always)]
    pub fn wupen(&self) -> WUPEN_R {
        WUPEN_R::new(((self.bits >> 3) & 1) != 0)
    }
    ///Bit 8 - Rx analog filter enable Setting the bit enables the Rx analog filter required for optimum Power Delivery reception.
    #[inline(always)]
    pub fn rxafilten(&self) -> RXAFILTEN_R {
        RXAFILTEN_R::new(((self.bits >> 8) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CFGR2")
            .field("rxfiltdis", &self.rxfiltdis())
            .field("rxfilt2n3", &self.rxfilt2n3())
            .field("forceclk", &self.forceclk())
            .field("wupen", &self.wupen())
            .field("rxafilten", &self.rxafilten())
            .finish()
    }
}
impl W {
    ///Bit 0 - BMC decoder Rx pre-filter enable The sampling clock is that of the receiver (that is, after pre-scaler).
    #[inline(always)]
    pub fn rxfiltdis(&mut self) -> RXFILTDIS_W<CFGR2rs> {
        RXFILTDIS_W::new(self, 0)
    }
    ///Bit 1 - BMC decoder Rx pre-filter sampling method Number of consistent consecutive samples before confirming a new value.
    #[inline(always)]
    pub fn rxfilt2n3(&mut self) -> RXFILT2N3_W<CFGR2rs> {
        RXFILT2N3_W::new(self, 1)
    }
    ///Bit 2 - Force ClkReq clock request
    #[inline(always)]
    pub fn forceclk(&mut self) -> FORCECLK_W<CFGR2rs> {
        FORCECLK_W::new(self, 2)
    }
    ///Bit 3 - Wakeup from Stop mode enable Setting the bit enables the UCPD_ASYNC_INT signal.
    #[inline(always)]
    pub fn wupen(&mut self) -> WUPEN_W<CFGR2rs> {
        WUPEN_W::new(self, 3)
    }
    ///Bit 8 - Rx analog filter enable Setting the bit enables the Rx analog filter required for optimum Power Delivery reception.
    #[inline(always)]
    pub fn rxafilten(&mut self) -> RXAFILTEN_W<CFGR2rs> {
        RXAFILTEN_W::new(self, 8)
    }
}
/**UCPD configuration register 2

You can [`read`](crate::Reg::read) this register and get [`cfgr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct CFGR2rs;
impl crate::RegisterSpec for CFGR2rs {
    type Ux = u32;
}
///`read()` method returns [`cfgr2::R`](R) reader structure
impl crate::Readable for CFGR2rs {}
///`write(|w| ..)` method takes [`cfgr2::W`](W) writer structure
impl crate::Writable for CFGR2rs {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
///`reset()` method sets CFGR2 to value 0
impl crate::Resettable for CFGR2rs {
    const RESET_VALUE: u32 = 0;
}
