///Register `IMR2` reader
pub type R = crate::R<IMR2rs>;
///Register `IMR2` writer
pub type W = crate::W<IMR2rs>;
/**CPU wake-up with interrupt mask on event input x

Value on reset: 1*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum IM32 {
    ///0: Interrupt request line is masked
    Masked = 0,
    ///1: Interrupt request line is unmasked
    Unmasked = 1,
}
impl From<IM32> for bool {
    #[inline(always)]
    fn from(variant: IM32) -> Self {
        variant as u8 != 0
    }
}
///Field `IM32` reader - CPU wake-up with interrupt mask on event input x
pub type IM32_R = crate::BitReader<IM32>;
impl IM32_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> IM32 {
        match self.bits {
            false => IM32::Masked,
            true => IM32::Unmasked,
        }
    }
    ///Interrupt request line is masked
    #[inline(always)]
    pub fn is_masked(&self) -> bool {
        *self == IM32::Masked
    }
    ///Interrupt request line is unmasked
    #[inline(always)]
    pub fn is_unmasked(&self) -> bool {
        *self == IM32::Unmasked
    }
}
///Field `IM32` writer - CPU wake-up with interrupt mask on event input x
pub type IM32_W<'a, REG> = crate::BitWriter<'a, REG, IM32>;
impl<'a, REG> IM32_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///Interrupt request line is masked
    #[inline(always)]
    pub fn masked(self) -> &'a mut crate::W<REG> {
        self.variant(IM32::Masked)
    }
    ///Interrupt request line is unmasked
    #[inline(always)]
    pub fn unmasked(self) -> &'a mut crate::W<REG> {
        self.variant(IM32::Unmasked)
    }
}
///Field `IM33` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM33_R;
///Field `IM34` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM34_R;
///Field `IM35` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM35_R;
///Field `IM36` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM36_R;
///Field `IM37` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM37_R;
///Field `IM38` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM38_R;
///Field `IM39` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM39_R;
///Field `IM40` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM40_R;
///Field `IM41` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM41_R;
///Field `IM42` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM42_R;
///Field `IM43` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM43_R;
///Field `IM44` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM44_R;
///Field `IM45` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM45_R;
///Field `IM46` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM46_R;
///Field `IM47` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM47_R;
///Field `IM48` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM48_R;
///Field `IM49` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM49_R;
///Field `IM50` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM50_R;
///Field `IM51` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM51_R;
///Field `IM52` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM52_R;
///Field `IM53` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM53_R;
///Field `IM54` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM54_R;
///Field `IM55` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM55_R;
///Field `IM56` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM56_R;
///Field `IM57` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM57_R;
///Field `IM58` reader - CPU wake-up with interrupt mask on event input x
pub use IM32_R as IM58_R;
///Field `IM33` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM33_W;
///Field `IM34` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM34_W;
///Field `IM35` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM35_W;
///Field `IM36` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM36_W;
///Field `IM37` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM37_W;
///Field `IM38` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM38_W;
///Field `IM39` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM39_W;
///Field `IM40` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM40_W;
///Field `IM41` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM41_W;
///Field `IM42` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM42_W;
///Field `IM43` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM43_W;
///Field `IM44` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM44_W;
///Field `IM45` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM45_W;
///Field `IM46` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM46_W;
///Field `IM47` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM47_W;
///Field `IM48` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM48_W;
///Field `IM49` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM49_W;
///Field `IM50` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM50_W;
///Field `IM51` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM51_W;
///Field `IM52` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM52_W;
///Field `IM53` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM53_W;
///Field `IM54` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM54_W;
///Field `IM55` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM55_W;
///Field `IM56` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM56_W;
///Field `IM57` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM57_W;
///Field `IM58` writer - CPU wake-up with interrupt mask on event input x
pub use IM32_W as IM58_W;
impl R {
    ///Bit 0 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im32(&self) -> IM32_R {
        IM32_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im33(&self) -> IM33_R {
        IM33_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im34(&self) -> IM34_R {
        IM34_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 3 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im35(&self) -> IM35_R {
        IM35_R::new(((self.bits >> 3) & 1) != 0)
    }
    ///Bit 4 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im36(&self) -> IM36_R {
        IM36_R::new(((self.bits >> 4) & 1) != 0)
    }
    ///Bit 5 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im37(&self) -> IM37_R {
        IM37_R::new(((self.bits >> 5) & 1) != 0)
    }
    ///Bit 6 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im38(&self) -> IM38_R {
        IM38_R::new(((self.bits >> 6) & 1) != 0)
    }
    ///Bit 7 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im39(&self) -> IM39_R {
        IM39_R::new(((self.bits >> 7) & 1) != 0)
    }
    ///Bit 8 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im40(&self) -> IM40_R {
        IM40_R::new(((self.bits >> 8) & 1) != 0)
    }
    ///Bit 9 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im41(&self) -> IM41_R {
        IM41_R::new(((self.bits >> 9) & 1) != 0)
    }
    ///Bit 10 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im42(&self) -> IM42_R {
        IM42_R::new(((self.bits >> 10) & 1) != 0)
    }
    ///Bit 11 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im43(&self) -> IM43_R {
        IM43_R::new(((self.bits >> 11) & 1) != 0)
    }
    ///Bit 12 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im44(&self) -> IM44_R {
        IM44_R::new(((self.bits >> 12) & 1) != 0)
    }
    ///Bit 13 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im45(&self) -> IM45_R {
        IM45_R::new(((self.bits >> 13) & 1) != 0)
    }
    ///Bit 14 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im46(&self) -> IM46_R {
        IM46_R::new(((self.bits >> 14) & 1) != 0)
    }
    ///Bit 15 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im47(&self) -> IM47_R {
        IM47_R::new(((self.bits >> 15) & 1) != 0)
    }
    ///Bit 16 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im48(&self) -> IM48_R {
        IM48_R::new(((self.bits >> 16) & 1) != 0)
    }
    ///Bit 17 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im49(&self) -> IM49_R {
        IM49_R::new(((self.bits >> 17) & 1) != 0)
    }
    ///Bit 18 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im50(&self) -> IM50_R {
        IM50_R::new(((self.bits >> 18) & 1) != 0)
    }
    ///Bit 19 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im51(&self) -> IM51_R {
        IM51_R::new(((self.bits >> 19) & 1) != 0)
    }
    ///Bit 20 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im52(&self) -> IM52_R {
        IM52_R::new(((self.bits >> 20) & 1) != 0)
    }
    ///Bit 21 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im53(&self) -> IM53_R {
        IM53_R::new(((self.bits >> 21) & 1) != 0)
    }
    ///Bit 22 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im54(&self) -> IM54_R {
        IM54_R::new(((self.bits >> 22) & 1) != 0)
    }
    ///Bit 23 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im55(&self) -> IM55_R {
        IM55_R::new(((self.bits >> 23) & 1) != 0)
    }
    ///Bit 24 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im56(&self) -> IM56_R {
        IM56_R::new(((self.bits >> 24) & 1) != 0)
    }
    ///Bit 25 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im57(&self) -> IM57_R {
        IM57_R::new(((self.bits >> 25) & 1) != 0)
    }
    ///Bit 26 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im58(&self) -> IM58_R {
        IM58_R::new(((self.bits >> 26) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IMR2")
            .field("im32", &self.im32())
            .field("im33", &self.im33())
            .field("im34", &self.im34())
            .field("im35", &self.im35())
            .field("im36", &self.im36())
            .field("im37", &self.im37())
            .field("im38", &self.im38())
            .field("im39", &self.im39())
            .field("im40", &self.im40())
            .field("im41", &self.im41())
            .field("im42", &self.im42())
            .field("im43", &self.im43())
            .field("im44", &self.im44())
            .field("im45", &self.im45())
            .field("im46", &self.im46())
            .field("im47", &self.im47())
            .field("im48", &self.im48())
            .field("im49", &self.im49())
            .field("im50", &self.im50())
            .field("im51", &self.im51())
            .field("im52", &self.im52())
            .field("im53", &self.im53())
            .field("im54", &self.im54())
            .field("im55", &self.im55())
            .field("im56", &self.im56())
            .field("im57", &self.im57())
            .field("im58", &self.im58())
            .finish()
    }
}
impl W {
    ///Bit 0 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im32(&mut self) -> IM32_W<IMR2rs> {
        IM32_W::new(self, 0)
    }
    ///Bit 1 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im33(&mut self) -> IM33_W<IMR2rs> {
        IM33_W::new(self, 1)
    }
    ///Bit 2 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im34(&mut self) -> IM34_W<IMR2rs> {
        IM34_W::new(self, 2)
    }
    ///Bit 3 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im35(&mut self) -> IM35_W<IMR2rs> {
        IM35_W::new(self, 3)
    }
    ///Bit 4 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im36(&mut self) -> IM36_W<IMR2rs> {
        IM36_W::new(self, 4)
    }
    ///Bit 5 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im37(&mut self) -> IM37_W<IMR2rs> {
        IM37_W::new(self, 5)
    }
    ///Bit 6 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im38(&mut self) -> IM38_W<IMR2rs> {
        IM38_W::new(self, 6)
    }
    ///Bit 7 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im39(&mut self) -> IM39_W<IMR2rs> {
        IM39_W::new(self, 7)
    }
    ///Bit 8 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im40(&mut self) -> IM40_W<IMR2rs> {
        IM40_W::new(self, 8)
    }
    ///Bit 9 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im41(&mut self) -> IM41_W<IMR2rs> {
        IM41_W::new(self, 9)
    }
    ///Bit 10 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im42(&mut self) -> IM42_W<IMR2rs> {
        IM42_W::new(self, 10)
    }
    ///Bit 11 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im43(&mut self) -> IM43_W<IMR2rs> {
        IM43_W::new(self, 11)
    }
    ///Bit 12 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im44(&mut self) -> IM44_W<IMR2rs> {
        IM44_W::new(self, 12)
    }
    ///Bit 13 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im45(&mut self) -> IM45_W<IMR2rs> {
        IM45_W::new(self, 13)
    }
    ///Bit 14 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im46(&mut self) -> IM46_W<IMR2rs> {
        IM46_W::new(self, 14)
    }
    ///Bit 15 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im47(&mut self) -> IM47_W<IMR2rs> {
        IM47_W::new(self, 15)
    }
    ///Bit 16 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im48(&mut self) -> IM48_W<IMR2rs> {
        IM48_W::new(self, 16)
    }
    ///Bit 17 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im49(&mut self) -> IM49_W<IMR2rs> {
        IM49_W::new(self, 17)
    }
    ///Bit 18 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im50(&mut self) -> IM50_W<IMR2rs> {
        IM50_W::new(self, 18)
    }
    ///Bit 19 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im51(&mut self) -> IM51_W<IMR2rs> {
        IM51_W::new(self, 19)
    }
    ///Bit 20 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im52(&mut self) -> IM52_W<IMR2rs> {
        IM52_W::new(self, 20)
    }
    ///Bit 21 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im53(&mut self) -> IM53_W<IMR2rs> {
        IM53_W::new(self, 21)
    }
    ///Bit 22 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im54(&mut self) -> IM54_W<IMR2rs> {
        IM54_W::new(self, 22)
    }
    ///Bit 23 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im55(&mut self) -> IM55_W<IMR2rs> {
        IM55_W::new(self, 23)
    }
    ///Bit 24 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im56(&mut self) -> IM56_W<IMR2rs> {
        IM56_W::new(self, 24)
    }
    ///Bit 25 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im57(&mut self) -> IM57_W<IMR2rs> {
        IM57_W::new(self, 25)
    }
    ///Bit 26 - CPU wake-up with interrupt mask on event input x
    #[inline(always)]
    pub fn im58(&mut self) -> IM58_W<IMR2rs> {
        IM58_W::new(self, 26)
    }
}
/**EXTI CPU wake-up with interrupt mask register 2

You can [`read`](crate::Reg::read) this register and get [`imr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct IMR2rs;
impl crate::RegisterSpec for IMR2rs {
    type Ux = u32;
}
///`read()` method returns [`imr2::R`](R) reader structure
impl crate::Readable for IMR2rs {}
///`write(|w| ..)` method takes [`imr2::W`](W) writer structure
impl crate::Writable for IMR2rs {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
///`reset()` method sets IMR2 to value 0x07db_bfff
impl crate::Resettable for IMR2rs {
    const RESET_VALUE: u32 = 0x07db_bfff;
}
