///Register `SECCFGR` reader
pub type R = crate::R<SECCFGRrs>;
///Register `SECCFGR` writer
pub type W = crate::W<SECCFGRrs>;
///Field `SBSSEC` reader - SBS clock control, memory-erase status register and compensation cell register security enable
pub type SBSSEC_R = crate::BitReader;
///Field `SBSSEC` writer - SBS clock control, memory-erase status register and compensation cell register security enable
pub type SBSSEC_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CLASSBSEC` reader - ClassB security enable
pub type CLASSBSEC_R = crate::BitReader;
///Field `CLASSBSEC` writer - ClassB security enable
pub type CLASSBSEC_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `FPUSEC` reader - FPU security enable
pub type FPUSEC_R = crate::BitReader;
///Field `FPUSEC` writer - FPU security enable
pub type FPUSEC_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 0 - SBS clock control, memory-erase status register and compensation cell register security enable
    #[inline(always)]
    pub fn sbssec(&self) -> SBSSEC_R {
        SBSSEC_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - ClassB security enable
    #[inline(always)]
    pub fn classbsec(&self) -> CLASSBSEC_R {
        CLASSBSEC_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 3 - FPU security enable
    #[inline(always)]
    pub fn fpusec(&self) -> FPUSEC_R {
        FPUSEC_R::new(((self.bits >> 3) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SECCFGR")
            .field("sbssec", &self.sbssec())
            .field("classbsec", &self.classbsec())
            .field("fpusec", &self.fpusec())
            .finish()
    }
}
impl W {
    ///Bit 0 - SBS clock control, memory-erase status register and compensation cell register security enable
    #[inline(always)]
    pub fn sbssec(&mut self) -> SBSSEC_W<SECCFGRrs> {
        SBSSEC_W::new(self, 0)
    }
    ///Bit 1 - ClassB security enable
    #[inline(always)]
    pub fn classbsec(&mut self) -> CLASSBSEC_W<SECCFGRrs> {
        CLASSBSEC_W::new(self, 1)
    }
    ///Bit 3 - FPU security enable
    #[inline(always)]
    pub fn fpusec(&mut self) -> FPUSEC_W<SECCFGRrs> {
        FPUSEC_W::new(self, 3)
    }
}
/**SBS security mode configuration control register

You can [`read`](crate::Reg::read) this register and get [`seccfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct SECCFGRrs;
impl crate::RegisterSpec for SECCFGRrs {
    type Ux = u32;
}
///`read()` method returns [`seccfgr::R`](R) reader structure
impl crate::Readable for SECCFGRrs {}
///`write(|w| ..)` method takes [`seccfgr::W`](W) writer structure
impl crate::Writable for SECCFGRrs {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
///`reset()` method sets SECCFGR to value 0
impl crate::Resettable for SECCFGRrs {
    const RESET_VALUE: u32 = 0;
}
