///Register `PRIVCFGR2` reader
pub type R = crate::R<PRIVCFGR2rs>;
///Register `PRIVCFGR2` writer
pub type W = crate::W<PRIVCFGR2rs>;
///Field `FDCAN1PRIV` reader - privileged access mode for FDCAN1
pub type FDCAN1PRIV_R = crate::BitReader;
///Field `FDCAN1PRIV` writer - privileged access mode for FDCAN1
pub type FDCAN1PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `FDCAN2PRIV` reader - privileged access mode for FDCAN2
pub type FDCAN2PRIV_R = crate::BitReader;
///Field `FDCAN2PRIV` writer - privileged access mode for FDCAN2
pub type FDCAN2PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `UCPDPRIV` reader - privileged access mode for UCPD
pub type UCPDPRIV_R = crate::BitReader;
///Field `UCPDPRIV` writer - privileged access mode for UCPD
pub type UCPDPRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TIM1PRIV` reader - privileged access mode for TIM1
pub type TIM1PRIV_R = crate::BitReader;
///Field `TIM1PRIV` writer - privileged access mode for TIM1
pub type TIM1PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `SPI1PRIV` reader - privileged access mode for SPI1
pub type SPI1PRIV_R = crate::BitReader;
///Field `SPI1PRIV` writer - privileged access mode for SPI1
pub type SPI1PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TIM8PRIV` reader - privileged access mode for TIM8
pub type TIM8PRIV_R = crate::BitReader;
///Field `TIM8PRIV` writer - privileged access mode for TIM8
pub type TIM8PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `USART1PRIV` reader - privileged access mode for USART1
pub type USART1PRIV_R = crate::BitReader;
///Field `USART1PRIV` writer - privileged access mode for USART1
pub type USART1PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TIM15PRIV` reader - privileged access mode for TIM15
pub type TIM15PRIV_R = crate::BitReader;
///Field `TIM15PRIV` writer - privileged access mode for TIM15
pub type TIM15PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `SPI4PRIV` reader - privileged access mode for SPI4
pub type SPI4PRIV_R = crate::BitReader;
///Field `SPI4PRIV` writer - privileged access mode for SPI4
pub type SPI4PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `SPI6PRIV` reader - privileged access mode for SPI6
pub type SPI6PRIV_R = crate::BitReader;
///Field `SPI6PRIV` writer - privileged access mode for SPI6
pub type SPI6PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `SAI1PRIV` reader - privileged access mode for SAI1
pub type SAI1PRIV_R = crate::BitReader;
///Field `SAI1PRIV` writer - privileged access mode for SAI1
pub type SAI1PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `SAI2PRIV` reader - privileged access mode for SAI2
pub type SAI2PRIV_R = crate::BitReader;
///Field `SAI2PRIV` writer - privileged access mode for SAI2
pub type SAI2PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `USBPRIV` reader - privileged access mode for USB
pub type USBPRIV_R = crate::BitReader;
///Field `USBPRIV` writer - privileged access mode for USB
pub type USBPRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `LPUART1PRIV` reader - privileged access mode for LPUART
pub type LPUART1PRIV_R = crate::BitReader;
///Field `LPUART1PRIV` writer - privileged access mode for LPUART
pub type LPUART1PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `I2C3PRIV` reader - privileged access mode for I2C3
pub type I2C3PRIV_R = crate::BitReader;
///Field `I2C3PRIV` writer - privileged access mode for I2C3
pub type I2C3PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `LPTIM1PRIV` reader - privileged access mode for LPTIM1
pub type LPTIM1PRIV_R = crate::BitReader;
///Field `LPTIM1PRIV` writer - privileged access mode for LPTIM1
pub type LPTIM1PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `LPTIM3PRIV` reader - privileged access mode for LPTIM3
pub type LPTIM3PRIV_R = crate::BitReader;
///Field `LPTIM3PRIV` writer - privileged access mode for LPTIM3
pub type LPTIM3PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `LPTIM4PRIV` reader - privileged access mode for LPTIM4
pub type LPTIM4PRIV_R = crate::BitReader;
///Field `LPTIM4PRIV` writer - privileged access mode for LPTIM4
pub type LPTIM4PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `LPTIM5PRIV` reader - privileged access mode for LPTIM5
pub type LPTIM5PRIV_R = crate::BitReader;
///Field `LPTIM5PRIV` writer - privileged access mode for LPTIM5
pub type LPTIM5PRIV_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 0 - privileged access mode for FDCAN1
    #[inline(always)]
    pub fn fdcan1priv(&self) -> FDCAN1PRIV_R {
        FDCAN1PRIV_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - privileged access mode for FDCAN2
    #[inline(always)]
    pub fn fdcan2priv(&self) -> FDCAN2PRIV_R {
        FDCAN2PRIV_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - privileged access mode for UCPD
    #[inline(always)]
    pub fn ucpdpriv(&self) -> UCPDPRIV_R {
        UCPDPRIV_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 8 - privileged access mode for TIM1
    #[inline(always)]
    pub fn tim1priv(&self) -> TIM1PRIV_R {
        TIM1PRIV_R::new(((self.bits >> 8) & 1) != 0)
    }
    ///Bit 9 - privileged access mode for SPI1
    #[inline(always)]
    pub fn spi1priv(&self) -> SPI1PRIV_R {
        SPI1PRIV_R::new(((self.bits >> 9) & 1) != 0)
    }
    ///Bit 10 - privileged access mode for TIM8
    #[inline(always)]
    pub fn tim8priv(&self) -> TIM8PRIV_R {
        TIM8PRIV_R::new(((self.bits >> 10) & 1) != 0)
    }
    ///Bit 11 - privileged access mode for USART1
    #[inline(always)]
    pub fn usart1priv(&self) -> USART1PRIV_R {
        USART1PRIV_R::new(((self.bits >> 11) & 1) != 0)
    }
    ///Bit 12 - privileged access mode for TIM15
    #[inline(always)]
    pub fn tim15priv(&self) -> TIM15PRIV_R {
        TIM15PRIV_R::new(((self.bits >> 12) & 1) != 0)
    }
    ///Bit 15 - privileged access mode for SPI4
    #[inline(always)]
    pub fn spi4priv(&self) -> SPI4PRIV_R {
        SPI4PRIV_R::new(((self.bits >> 15) & 1) != 0)
    }
    ///Bit 16 - privileged access mode for SPI6
    #[inline(always)]
    pub fn spi6priv(&self) -> SPI6PRIV_R {
        SPI6PRIV_R::new(((self.bits >> 16) & 1) != 0)
    }
    ///Bit 17 - privileged access mode for SAI1
    #[inline(always)]
    pub fn sai1priv(&self) -> SAI1PRIV_R {
        SAI1PRIV_R::new(((self.bits >> 17) & 1) != 0)
    }
    ///Bit 18 - privileged access mode for SAI2
    #[inline(always)]
    pub fn sai2priv(&self) -> SAI2PRIV_R {
        SAI2PRIV_R::new(((self.bits >> 18) & 1) != 0)
    }
    ///Bit 19 - privileged access mode for USB
    #[inline(always)]
    pub fn usbpriv(&self) -> USBPRIV_R {
        USBPRIV_R::new(((self.bits >> 19) & 1) != 0)
    }
    ///Bit 25 - privileged access mode for LPUART
    #[inline(always)]
    pub fn lpuart1priv(&self) -> LPUART1PRIV_R {
        LPUART1PRIV_R::new(((self.bits >> 25) & 1) != 0)
    }
    ///Bit 26 - privileged access mode for I2C3
    #[inline(always)]
    pub fn i2c3priv(&self) -> I2C3PRIV_R {
        I2C3PRIV_R::new(((self.bits >> 26) & 1) != 0)
    }
    ///Bit 28 - privileged access mode for LPTIM1
    #[inline(always)]
    pub fn lptim1priv(&self) -> LPTIM1PRIV_R {
        LPTIM1PRIV_R::new(((self.bits >> 28) & 1) != 0)
    }
    ///Bit 29 - privileged access mode for LPTIM3
    #[inline(always)]
    pub fn lptim3priv(&self) -> LPTIM3PRIV_R {
        LPTIM3PRIV_R::new(((self.bits >> 29) & 1) != 0)
    }
    ///Bit 30 - privileged access mode for LPTIM4
    #[inline(always)]
    pub fn lptim4priv(&self) -> LPTIM4PRIV_R {
        LPTIM4PRIV_R::new(((self.bits >> 30) & 1) != 0)
    }
    ///Bit 31 - privileged access mode for LPTIM5
    #[inline(always)]
    pub fn lptim5priv(&self) -> LPTIM5PRIV_R {
        LPTIM5PRIV_R::new(((self.bits >> 31) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PRIVCFGR2")
            .field("fdcan1priv", &self.fdcan1priv())
            .field("fdcan2priv", &self.fdcan2priv())
            .field("ucpdpriv", &self.ucpdpriv())
            .field("tim1priv", &self.tim1priv())
            .field("spi1priv", &self.spi1priv())
            .field("tim8priv", &self.tim8priv())
            .field("usart1priv", &self.usart1priv())
            .field("tim15priv", &self.tim15priv())
            .field("spi4priv", &self.spi4priv())
            .field("spi6priv", &self.spi6priv())
            .field("sai1priv", &self.sai1priv())
            .field("sai2priv", &self.sai2priv())
            .field("usbpriv", &self.usbpriv())
            .field("lpuart1priv", &self.lpuart1priv())
            .field("i2c3priv", &self.i2c3priv())
            .field("lptim1priv", &self.lptim1priv())
            .field("lptim3priv", &self.lptim3priv())
            .field("lptim4priv", &self.lptim4priv())
            .field("lptim5priv", &self.lptim5priv())
            .finish()
    }
}
impl W {
    ///Bit 0 - privileged access mode for FDCAN1
    #[inline(always)]
    pub fn fdcan1priv(&mut self) -> FDCAN1PRIV_W<PRIVCFGR2rs> {
        FDCAN1PRIV_W::new(self, 0)
    }
    ///Bit 1 - privileged access mode for FDCAN2
    #[inline(always)]
    pub fn fdcan2priv(&mut self) -> FDCAN2PRIV_W<PRIVCFGR2rs> {
        FDCAN2PRIV_W::new(self, 1)
    }
    ///Bit 2 - privileged access mode for UCPD
    #[inline(always)]
    pub fn ucpdpriv(&mut self) -> UCPDPRIV_W<PRIVCFGR2rs> {
        UCPDPRIV_W::new(self, 2)
    }
    ///Bit 8 - privileged access mode for TIM1
    #[inline(always)]
    pub fn tim1priv(&mut self) -> TIM1PRIV_W<PRIVCFGR2rs> {
        TIM1PRIV_W::new(self, 8)
    }
    ///Bit 9 - privileged access mode for SPI1
    #[inline(always)]
    pub fn spi1priv(&mut self) -> SPI1PRIV_W<PRIVCFGR2rs> {
        SPI1PRIV_W::new(self, 9)
    }
    ///Bit 10 - privileged access mode for TIM8
    #[inline(always)]
    pub fn tim8priv(&mut self) -> TIM8PRIV_W<PRIVCFGR2rs> {
        TIM8PRIV_W::new(self, 10)
    }
    ///Bit 11 - privileged access mode for USART1
    #[inline(always)]
    pub fn usart1priv(&mut self) -> USART1PRIV_W<PRIVCFGR2rs> {
        USART1PRIV_W::new(self, 11)
    }
    ///Bit 12 - privileged access mode for TIM15
    #[inline(always)]
    pub fn tim15priv(&mut self) -> TIM15PRIV_W<PRIVCFGR2rs> {
        TIM15PRIV_W::new(self, 12)
    }
    ///Bit 15 - privileged access mode for SPI4
    #[inline(always)]
    pub fn spi4priv(&mut self) -> SPI4PRIV_W<PRIVCFGR2rs> {
        SPI4PRIV_W::new(self, 15)
    }
    ///Bit 16 - privileged access mode for SPI6
    #[inline(always)]
    pub fn spi6priv(&mut self) -> SPI6PRIV_W<PRIVCFGR2rs> {
        SPI6PRIV_W::new(self, 16)
    }
    ///Bit 17 - privileged access mode for SAI1
    #[inline(always)]
    pub fn sai1priv(&mut self) -> SAI1PRIV_W<PRIVCFGR2rs> {
        SAI1PRIV_W::new(self, 17)
    }
    ///Bit 18 - privileged access mode for SAI2
    #[inline(always)]
    pub fn sai2priv(&mut self) -> SAI2PRIV_W<PRIVCFGR2rs> {
        SAI2PRIV_W::new(self, 18)
    }
    ///Bit 19 - privileged access mode for USB
    #[inline(always)]
    pub fn usbpriv(&mut self) -> USBPRIV_W<PRIVCFGR2rs> {
        USBPRIV_W::new(self, 19)
    }
    ///Bit 25 - privileged access mode for LPUART
    #[inline(always)]
    pub fn lpuart1priv(&mut self) -> LPUART1PRIV_W<PRIVCFGR2rs> {
        LPUART1PRIV_W::new(self, 25)
    }
    ///Bit 26 - privileged access mode for I2C3
    #[inline(always)]
    pub fn i2c3priv(&mut self) -> I2C3PRIV_W<PRIVCFGR2rs> {
        I2C3PRIV_W::new(self, 26)
    }
    ///Bit 28 - privileged access mode for LPTIM1
    #[inline(always)]
    pub fn lptim1priv(&mut self) -> LPTIM1PRIV_W<PRIVCFGR2rs> {
        LPTIM1PRIV_W::new(self, 28)
    }
    ///Bit 29 - privileged access mode for LPTIM3
    #[inline(always)]
    pub fn lptim3priv(&mut self) -> LPTIM3PRIV_W<PRIVCFGR2rs> {
        LPTIM3PRIV_W::new(self, 29)
    }
    ///Bit 30 - privileged access mode for LPTIM4
    #[inline(always)]
    pub fn lptim4priv(&mut self) -> LPTIM4PRIV_W<PRIVCFGR2rs> {
        LPTIM4PRIV_W::new(self, 30)
    }
    ///Bit 31 - privileged access mode for LPTIM5
    #[inline(always)]
    pub fn lptim5priv(&mut self) -> LPTIM5PRIV_W<PRIVCFGR2rs> {
        LPTIM5PRIV_W::new(self, 31)
    }
}
/**GTZC1 TZSC privilege configuration register 2

You can [`read`](crate::Reg::read) this register and get [`privcfgr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`privcfgr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct PRIVCFGR2rs;
impl crate::RegisterSpec for PRIVCFGR2rs {
    type Ux = u32;
}
///`read()` method returns [`privcfgr2::R`](R) reader structure
impl crate::Readable for PRIVCFGR2rs {}
///`write(|w| ..)` method takes [`privcfgr2::W`](W) writer structure
impl crate::Writable for PRIVCFGR2rs {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
///`reset()` method sets PRIVCFGR2 to value 0
impl crate::Resettable for PRIVCFGR2rs {
    const RESET_VALUE: u32 = 0;
}
