///Register `M3ISR` reader
pub type R = crate::R<M3ISRrs>;
///Field `SEDC` reader - ECC single error detected and corrected
pub type SEDC_R = crate::BitReader;
///Field `DED` reader - ECC double error detected
pub type DED_R = crate::BitReader;
///Field `SRAMBUSY` reader - SRAM busy with erase operation
pub type SRAMBUSY_R = crate::BitReader;
impl R {
    ///Bit 0 - ECC single error detected and corrected
    #[inline(always)]
    pub fn sedc(&self) -> SEDC_R {
        SEDC_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - ECC double error detected
    #[inline(always)]
    pub fn ded(&self) -> DED_R {
        DED_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 8 - SRAM busy with erase operation
    #[inline(always)]
    pub fn srambusy(&self) -> SRAMBUSY_R {
        SRAMBUSY_R::new(((self.bits >> 8) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("M3ISR")
            .field("sedc", &self.sedc())
            .field("ded", &self.ded())
            .field("srambusy", &self.srambusy())
            .finish()
    }
}
/**RAMCFG memory interrupt status register

You can [`read`](crate::Reg::read) this register and get [`m3isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct M3ISRrs;
impl crate::RegisterSpec for M3ISRrs {
    type Ux = u32;
}
///`read()` method returns [`m3isr::R`](R) reader structure
impl crate::Readable for M3ISRrs {}
///`reset()` method sets M3ISR to value 0
impl crate::Resettable for M3ISRrs {
    const RESET_VALUE: u32 = 0;
}
